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https://github.com/silvervest/OpenFlops-W1D.git
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And we're done!
This is a first rev of the PCB, done "by eye" as similarly as possible as one of my boards. There are quite a few improvements that we can make...
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404e3a02db
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+22
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@@ -1,4 +1,4 @@
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update=gio 25 lug 2019 08:50:17 CEST
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update=gio 25 lug 2019 20:18:02 CEST
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version=1
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last_client=kicad
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[general]
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@@ -22,15 +22,21 @@ AllowMicroVias=0
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AllowBlindVias=0
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RequireCourtyardDefinitions=0
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ProhibitOverlappingCourtyards=1
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MinTrackWidth=0.2
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MinTrackWidth=0.16
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MinViaDiameter=0.4
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MinViaDrill=0.3
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MinMicroViaDiameter=0.2
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MinMicroViaDrill=0.09999999999999999
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MinHoleToHole=0.25
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TrackWidth1=0.25
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ViaDiameter1=0.8
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TrackWidth2=0.2
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TrackWidth3=0.25
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ViaDiameter1=0.6
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ViaDrill1=0.4
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ViaDiameter2=0.6
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ViaDrill2=0.4
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ViaDiameter3=0.8
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ViaDrill3=0.6
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dPairWidth1=0.2
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dPairGap1=0.25
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dPairViaGap1=0.25
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@@ -54,7 +60,7 @@ OthersTextSizeH=1
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OthersTextSizeThickness=0.15
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OthersTextItalic=0
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OthersTextUpright=1
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SolderMaskClearance=0.051
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SolderMaskClearance=0
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SolderMaskMinWidth=0.25
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SolderPasteClearance=0
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SolderPasteRatio=-0
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@@ -229,7 +235,7 @@ Enabled=0
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Name=Default
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Clearance=0.25
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TrackWidth=0.25
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ViaDiameter=0.8
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ViaDiameter=0.6
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ViaDrill=0.4
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uViaDiameter=0.3
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uViaDrill=0.1
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@@ -241,6 +247,17 @@ Name=Power
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Clearance=0.25
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TrackWidth=0.75
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ViaDiameter=0.8
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ViaDrill=0.6
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uViaDiameter=0.3
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uViaDrill=0.1
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dPairWidth=0.2
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dPairGap=0.25
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dPairViaGap=0.25
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[pcbnew/Netclasses/2]
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Name=uC
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Clearance=0.15
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TrackWidth=0.2
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ViaDiameter=0.6
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ViaDrill=0.4
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uViaDiameter=0.3
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uViaDrill=0.1
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