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2.24.1

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kraus
2018-10-11 07:59:12 +02:00
parent 0acf1d263b
commit 9dc5410a3a
3 changed files with 146 additions and 42 deletions
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README.md
+1 -1
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@@ -8,5 +8,5 @@ Description: https://github.com/olikraus/u8g2/wiki
Issue Tracker: https://github.com/olikraus/u8g2/issues
Download (2.24.0): https://github.com/olikraus/U8g2_Arduino/archive/master.zip
Download (2.24.1): https://github.com/olikraus/U8g2_Arduino/archive/master.zip
library.properties
+1 -1
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@@ -1,5 +1,5 @@
name=U8g2
version=2.24.0
version=2.24.1
author=oliver <olikraus@gmail.com>
maintainer=oliver <olikraus@gmail.com>
sentence=Monochrome LCD, OLED and eInk Library. Display controller: SSD1305, SSD1306, SSD1309, SSD1322, SSD1325, SSD1327, SSD1329, SSD1606, SSD1607, SH1106, SH1107, SH1108, SH1122, T6963, RA8835, LC7981, PCD8544, PCF8812, HX1230, UC1601, UC1604, UC1608, UC1610, UC1611, UC1701, ST7565, ST7567, ST7588, ST75256, NT7534, IST3020, ST7920, LD7032, KS0108, SED1520, SBN1661, IL3820, MAX7219. Interfaces: I2C, SPI, Parallel.
src/clib/u8x8_d_ssd1325.c
+144 -40
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@@ -44,46 +44,6 @@
/* http://www.newhavendisplay.com/app_notes/OLED_2_7_12864.txt */
static const uint8_t u8x8_d_ssd1325_128x64_nhd_init_seq[] = {
U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
U8X8_C(0x0ae), /* display off */
U8X8_CA(0x0b3, 0x091), /* set display clock divide ratio/oscillator frequency (set clock as 135 frames/sec) */
U8X8_CA(0x0a8, 0x03f), /* multiplex ratio: 0x03f * 1/64 duty */
U8X8_CA(0x0a2, 0x04c), /* display offset, shift mapping ram counter */
U8X8_CA(0x0a1, 0x000), /* display start line */
U8X8_CA(0x0ad, 0x002), /* master configuration: disable embedded DC-DC, enable internal VCOMH */
U8X8_CA(0x0a0, 0x052), /* remap configuration, horizontal address increment (bit 2 = 0), enable nibble remap (upper nibble is left, bit 1 = 1) */
U8X8_C(0x086), /* full current range (0x084, 0x085, 0x086) */
U8X8_C(0x0b8), /* set gray scale table */
U8X8_A(0x001), /* */
U8X8_A(0x011), /* */
U8X8_A(0x022), /* */
U8X8_A(0x032), /* */
U8X8_A(0x043), /* */
U8X8_A(0x054), /* */
U8X8_A(0x065), /* */
U8X8_A(0x076), /* */
U8X8_CA(0x081, 0x070), /* contrast, brightness, 0..128, Newhaven: 0x040 */
U8X8_CA(0x0b2, 0x051), /* frame frequency (row period) */
U8X8_CA(0x0b1, 0x055), /* phase length */
U8X8_CA(0x0bc, 0x010), /* pre-charge voltage level */
U8X8_CA(0x0b4, 0x002), /* set pre-charge compensation level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
U8X8_CA(0x0b0, 0x028), /* enable pre-charge compensation (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
U8X8_CA(0x0be, 0x01c), /* VCOMH voltage */
U8X8_CA(0x0bf, 0x002|0x00d), /* VSL voltage level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
U8X8_C(0x0a4), /* normal display mode */
U8X8_CA(0x023, 0x003), /* graphics accelleration: fill pixel */
U8X8_END_TRANSFER(), /* disable chip */
U8X8_END() /* end of sequence */
};
static const uint8_t u8x8_d_ssd1325_128x64_nhd_powersave0_seq[] = {
U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
U8X8_C(0x0af), /* display on */
@@ -166,16 +126,21 @@ static uint8_t u8x8_d_ssd1325_128x64_generic(u8x8_t *u8x8, uint8_t msg, uint8_t
u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1325_128x64_nhd_display_info);
break;
*/
/* handled by the calling function
case U8X8_MSG_DISPLAY_INIT:
u8x8_d_helper_display_init(u8x8);
u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1325_128x64_nhd_init_seq);
break;
*/
case U8X8_MSG_DISPLAY_SET_POWER_SAVE:
if ( arg_int == 0 )
u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1325_128x64_nhd_powersave0_seq);
else
u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1325_128x64_nhd_powersave1_seq);
break;
/* handled by the calling function
case U8X8_MSG_DISPLAY_SET_FLIP_MODE:
if ( arg_int == 0 )
{
@@ -188,6 +153,7 @@ static uint8_t u8x8_d_ssd1325_128x64_generic(u8x8_t *u8x8, uint8_t msg, uint8_t
u8x8->x_offset = u8x8->display_info->flipmode_x_offset;
}
break;
*/
#ifdef U8X8_WITH_SET_CONTRAST
case U8X8_MSG_DISPLAY_SET_CONTRAST:
u8x8_cad_StartTransfer(u8x8);
@@ -246,6 +212,8 @@ static uint8_t u8x8_d_ssd1325_128x64_generic(u8x8_t *u8x8, uint8_t msg, uint8_t
//x += 4;
arg_int--;
} while( arg_int > 0 );
u8x8_cad_SendCmd(u8x8, 0xe3); // no-op needs to be sent after last byte before cs is toggled.
u8x8_cad_EndTransfer(u8x8);
break;
@@ -257,6 +225,46 @@ static uint8_t u8x8_d_ssd1325_128x64_generic(u8x8_t *u8x8, uint8_t msg, uint8_t
/*===================================================================*/
/* http://www.newhavendisplay.com/app_notes/OLED_2_7_12864.txt */
static const uint8_t u8x8_d_ssd1325_128x64_nhd_init_seq[] = {
U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
U8X8_C(0x0ae), /* display off */
U8X8_CA(0x0b3, 0x091), /* set display clock divide ratio/oscillator frequency (set clock as 135 frames/sec) */
U8X8_CA(0x0a8, 0x03f), /* multiplex ratio: 0x03f * 1/64 duty */
U8X8_CA(0x0a2, 0x04c), /* display offset, shift mapping ram counter */
U8X8_CA(0x0a1, 0x000), /* display start line */
U8X8_CA(0x0ad, 0x002), /* master configuration: disable embedded DC-DC, enable internal VCOMH */
U8X8_CA(0x0a0, 0x052), /* remap configuration, horizontal address increment (bit 2 = 0), enable nibble remap (upper nibble is left, bit 1 = 1) */
U8X8_C(0x086), /* full current range (0x084, 0x085, 0x086) */
U8X8_C(0x0b8), /* set gray scale table */
U8X8_A(0x001), /* */
U8X8_A(0x011), /* */
U8X8_A(0x022), /* */
U8X8_A(0x032), /* */
U8X8_A(0x043), /* */
U8X8_A(0x054), /* */
U8X8_A(0x065), /* */
U8X8_A(0x076), /* */
U8X8_CA(0x081, 0x070), /* contrast, brightness, 0..128, Newhaven: 0x040 */
U8X8_CA(0x0b2, 0x051), /* frame frequency (row period) */
U8X8_CA(0x0b1, 0x055), /* phase length */
U8X8_CA(0x0bc, 0x010), /* pre-charge voltage level */
U8X8_CA(0x0b4, 0x002), /* set pre-charge compensation level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
U8X8_CA(0x0b0, 0x028), /* enable pre-charge compensation (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
U8X8_CA(0x0be, 0x01c), /* VCOMH voltage */
U8X8_CA(0x0bf, 0x002|0x00d), /* VSL voltage level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
U8X8_C(0x0a4), /* normal display mode */
U8X8_CA(0x023, 0x003), /* graphics accelleration: fill pixel */
U8X8_END_TRANSFER(), /* disable chip */
U8X8_END() /* end of sequence */
};
static const u8x8_display_info_t u8x8_nhd_ssd1325_128x64_display_info =
{
/* chip_enable_level = */ 0,
@@ -288,10 +296,86 @@ uint8_t u8x8_d_ssd1325_nhd_128x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, vo
u8x8_d_helper_display_setup_memory(u8x8, &u8x8_nhd_ssd1325_128x64_display_info);
return 1;
}
else if ( msg == U8X8_MSG_DISPLAY_INIT )
{
u8x8_d_helper_display_init(u8x8);
u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1325_128x64_nhd_init_seq);
return 1;
}
else if ( msg == U8X8_MSG_DISPLAY_SET_FLIP_MODE )
{
if ( arg_int == 0 )
{
u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1325_128x64_nhd_flip0_seq);
u8x8->x_offset = u8x8->display_info->default_x_offset;
}
else
{
u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1325_128x64_nhd_flip1_seq);
u8x8->x_offset = u8x8->display_info->flipmode_x_offset;
}
return 1;
}
return u8x8_d_ssd1325_128x64_generic(u8x8, msg, arg_int, arg_ptr);
}
/*===================================================================*/
/* OSRAM Pictiva 128x64 OLED */
/* https://github.com/olikraus/u8g2/issues/720 */
static const uint8_t u8x8_d_ssd0323_os128064_init_seq[] = {
U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
U8X8_C(0x0ae), /* display off */
U8X8_CA(0x0b3, 0x091), /* set display clock divide ratio/oscillator frequency (set clock as 135 frames/sec) */
U8X8_CA(0x0a8, 0x03f), /* multiplex ratio: 0x03f * 1/64 duty */
U8X8_CA(0x0a2, 0x040), /* display offset, shift mapping ram counter */
U8X8_CA(0x0a1, 0x000), /* display start line */
U8X8_CA(0x0ad, 0x002), /* master configuration: disable embedded DC-DC, enable internal VCOMH */
U8X8_CA(0x0a0, 0x052), /* remap configuration, horizontal address increment (bit 2 = 0), enable nibble remap (upper nibble is left, bit 1 = 1) */
U8X8_C(0x086), /* full current range (0x084, 0x085, 0x086) */
U8X8_C(0x0b8), /* set gray scale table */
U8X8_A(0x001), /* */
U8X8_A(0x011), /* */
U8X8_A(0x022), /* */
U8X8_A(0x032), /* */
U8X8_A(0x043), /* */
U8X8_A(0x054), /* */
U8X8_A(0x065), /* */
U8X8_A(0x076), /* */
U8X8_CA(0x081, 0x070), /* contrast, brightness, 0..128, Newhaven: 0x040 */
U8X8_CA(0x0b2, 0x051), /* frame frequency (row period) */
U8X8_CA(0x0b1, 0x055), /* phase length */
U8X8_CA(0x0bc, 0x010), /* pre-charge voltage level */
U8X8_CA(0x0b4, 0x002), /* set pre-charge compensation level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
U8X8_CA(0x0b0, 0x028), /* enable pre-charge compensation (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
U8X8_CA(0x0be, 0x01c), /* VCOMH voltage */
U8X8_CA(0x0bf, 0x002|0x00d), /* VSL voltage level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
U8X8_C(0x0a4), /* normal display mode */
U8X8_CA(0x023, 0x003), /* graphics accelleration: fill pixel */
U8X8_END_TRANSFER(), /* disable chip */
U8X8_END() /* end of sequence */
};
static const uint8_t u8x8_d_ssd0323_os128064_flip0_seq[] = {
U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
U8X8_CA(0x0a0, 0x052), /* remap */
U8X8_CA(0x0a2, 0x040), /* display offset, shift mapping ram counter */
U8X8_END_TRANSFER(), /* disable chip */
U8X8_END() /* end of sequence */
};
static const uint8_t u8x8_d_ssd0323_os128064_flip1_seq[] = {
U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
U8X8_CA(0x0a0, 0x041), /* remap */
U8X8_CA(0x0a2, 0x050), /* display offset, shift mapping ram counter */
U8X8_END_TRANSFER(), /* disable chip */
U8X8_END() /* end of sequence */
};
static const u8x8_display_info_t u8x8_ssd0323_os128064_display_info =
{
@@ -324,6 +408,26 @@ uint8_t u8x8_d_ssd0323_os128064(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void
u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd0323_os128064_display_info);
return 1;
}
else if ( msg == U8X8_MSG_DISPLAY_INIT )
{
u8x8_d_helper_display_init(u8x8);
u8x8_cad_SendSequence(u8x8, u8x8_d_ssd0323_os128064_init_seq);
return 1;
}
else if ( msg == U8X8_MSG_DISPLAY_SET_FLIP_MODE )
{
if ( arg_int == 0 )
{
u8x8_cad_SendSequence(u8x8, u8x8_d_ssd0323_os128064_flip0_seq);
u8x8->x_offset = u8x8->display_info->default_x_offset;
}
else
{
u8x8_cad_SendSequence(u8x8, u8x8_d_ssd0323_os128064_flip1_seq);
u8x8->x_offset = u8x8->display_info->flipmode_x_offset;
}
return 1;
}
return u8x8_d_ssd1325_128x64_generic(u8x8, msg, arg_int, arg_ptr);
}