[RTC SRAM] Fix initialization error causing reboots at read

This commit is contained in:
Ton Huisman
2026-08-21 15:23:53 +02:00
parent 899e557c18
commit 146904e5be
2 changed files with 24 additions and 11 deletions
+5 -5
View File
@@ -300,7 +300,7 @@ public:
void writenvram(uint8_t address, uint8_t *buf, uint8_t size);
protected:
TwoWire *RTCWireBus;
TwoWire *RTCWireBus = nullptr;
};
/** DS3231 SQW pin mode settings */
@@ -362,7 +362,7 @@ public:
void writenvram(uint8_t address, uint8_t *buf, uint8_t size);
protected:
TwoWire *RTCWireBus;
TwoWire *RTCWireBus = nullptr;
};
/** PCF8523 INT/SQW pin mode settings */
@@ -433,7 +433,7 @@ public:
void calibrate(Pcf8523OffsetMode mode, int8_t offset);
protected:
TwoWire *RTCWireBus;
TwoWire *RTCWireBus = nullptr;
};
/** PCF8563 CLKOUT pin mode settings */
@@ -464,7 +464,7 @@ public:
void writeSqwPinMode(Pcf8563SqwPinMode mode);
protected:
TwoWire *RTCWireBus;
TwoWire *RTCWireBus = nullptr;
};
/**************************************************************************/
@@ -487,7 +487,7 @@ public:
void writenvram(uint8_t address, uint8_t *buf, uint8_t size);
protected:
TwoWire *RTCWireBus;
TwoWire *RTCWireBus = nullptr;
uint8_t _addr = PCF8583_ADDRESS;
};
+19 -6
View File
@@ -179,11 +179,13 @@ bool writeRTCSRAMSlot(uint32_t slot,
case ExtTimeSource_e::DS1307:
{
RTC_DS1307 rtc;
if (!rtc.begin()) { return false; }
rtc.readnvram(_b, sizeof_rtcsram_slot, addr);
STOP_TIMER(READ_RTC_SLOT);
const SRAM_STORAGE_FLOAT_TYPE oldData = *(SRAM_STORAGE_FLOAT_TYPE *)&_b[0];
if (!essentiallyEqual(oldData, data)) {
if (isnan(oldData) || !essentiallyEqual(oldData, data)) {
rtc.writenvram(addr, (uint8_t *)&data, sizeof_rtcsram_slot);
STOP_TIMER(WRITE_RTC_SLOT);
}
@@ -192,11 +194,13 @@ bool writeRTCSRAMSlot(uint32_t slot,
case ExtTimeSource_e::DS3232:
{
RTC_DS3231 rtc;
if (!rtc.begin()) { return false; }
rtc.readnvram(_b, sizeof_rtcsram_slot, addr);
STOP_TIMER(READ_RTC_SLOT);
const SRAM_STORAGE_FLOAT_TYPE oldData = *(SRAM_STORAGE_FLOAT_TYPE *)&_b[0];
if (!essentiallyEqual(oldData, data)) {
if (isnan(oldData) || !essentiallyEqual(oldData, data)) {
rtc.writenvram(addr, (uint8_t *)&data, sizeof_rtcsram_slot);
STOP_TIMER(WRITE_RTC_SLOT);
}
@@ -212,11 +216,12 @@ bool writeRTCSRAMSlot(uint32_t slot,
rtc.altAddress(); // Set alternative address (0x51)
}
if (!rtc.begin()) { return false; }
rtc.readnvram(_b, sizeof_rtcsram_slot, addr);
STOP_TIMER(READ_RTC_SLOT);
const SRAM_STORAGE_FLOAT_TYPE oldData = *(SRAM_STORAGE_FLOAT_TYPE *)&_b[0];
if (!essentiallyEqual(oldData, data)) {
if (isnan(oldData) || !essentiallyEqual(oldData, data)) {
rtc.writenvram(addr, (uint8_t *)&data, sizeof_rtcsram_slot);
STOP_TIMER(WRITE_RTC_SLOT);
}
@@ -250,14 +255,20 @@ SRAM_STORAGE_FLOAT_TYPE readRTCSRAMSlot(uint32_t slot) {
case ExtTimeSource_e::DS1307:
{
RTC_DS1307 rtc;
rtc.readnvram(_b, sizeof_rtcsram_slot, addr);
if (rtc.begin()) {
rtc.readnvram(_b, sizeof_rtcsram_slot, addr);
}
STOP_TIMER(READ_RTC_SLOT);
return *(SRAM_STORAGE_FLOAT_TYPE *)&_b[0];
}
case ExtTimeSource_e::DS3232:
{
RTC_DS3231 rtc;
rtc.readnvram(_b, sizeof_rtcsram_slot, addr);
if (rtc.begin()) {
rtc.readnvram(_b, sizeof_rtcsram_slot, addr);
}
STOP_TIMER(READ_RTC_SLOT);
return *(SRAM_STORAGE_FLOAT_TYPE *)&_b[0];
}
@@ -271,7 +282,9 @@ SRAM_STORAGE_FLOAT_TYPE readRTCSRAMSlot(uint32_t slot) {
rtc.altAddress(); // Set alternative address (0x51)
}
rtc.readnvram(_b, sizeof_rtcsram_slot, addr);
if (rtc.begin()) {
rtc.readnvram(_b, sizeof_rtcsram_slot, addr);
}
STOP_TIMER(READ_RTC_SLOT);
return *(SRAM_STORAGE_FLOAT_TYPE *)&_b[0];
}