mirror of
https://github.com/letscontrolit/ESPEasy.git
synced 2026-07-28 04:07:47 +00:00
[GPIO info] Add hardware/GPIO specifics for ESP32-C3/S3
This commit is contained in:
TD-er
@@ -5,7 +5,7 @@
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"memory_type": "dio_qspi"
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},
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"core": "esp32",
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"extra_flags": "-DARDUINO_ESP32_DEV -DBOARD_HAS_PSRAM -DHAS_PSRAM_FIX -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw -DARDUINO_USB_CDC_ON_BOOT=0 -DESP32_4M",
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"extra_flags": "-DARDUINO_ESP32_DEV -DBOARD_HAS_PSRAM -DHAS_PSRAM_FIX -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw -DARDUINO_USB_CDC_ON_BOOT=0 -DESP32_4M -DESP32_CLASIC",
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"f_cpu": "240000000L",
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"f_flash": "80000000L",
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"flash_mode": "dio",
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@@ -5,7 +5,7 @@
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"memory_type": "dio_qspi"
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},
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"core": "esp32",
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"extra_flags": "-DARDUINO_M5STACK_Core2 -DBOARD_HAS_PSRAM -DARDUINO_USB_CDC_ON_BOOT=0 -DESP32_16M",
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"extra_flags": "-DARDUINO_M5STACK_Core2 -DBOARD_HAS_PSRAM -DARDUINO_USB_CDC_ON_BOOT=0 -DESP32_16M -DESP32_CLASIC",
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"f_cpu": "240000000L",
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"f_flash": "80000000L",
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"flash_mode": "dio",
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@@ -5,7 +5,7 @@
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"memory_type": "dio_qspi"
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},
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"core": "esp32",
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"extra_flags": "-DARDUINO_ODROID_ESP32 -DBOARD_HAS_PSRAM -DHAS_PSRAM_FIX -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw -DARDUINO_USB_CDC_ON_BOOT=0 -DESP32_16M",
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"extra_flags": "-DARDUINO_ODROID_ESP32 -DBOARD_HAS_PSRAM -DHAS_PSRAM_FIX -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw -DARDUINO_USB_CDC_ON_BOOT=0 -DESP32_16M -DESP32_CLASIC",
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"f_cpu": "240000000L",
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"f_flash": "80000000L",
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"flash_mode": "dio",
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@@ -5,7 +5,7 @@
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"memory_type": "dio_qspi"
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},
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"core": "esp32",
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"extra_flags": "-DARDUINO_ESP32_DEV -DBOARD_HAS_PSRAM -DARDUINO_USB_CDC_ON_BOOT=0 -DESP32_16M",
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"extra_flags": "-DARDUINO_ESP32_DEV -DBOARD_HAS_PSRAM -DARDUINO_USB_CDC_ON_BOOT=0 -DESP32_16M -DESP32_CLASIC",
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"f_cpu": "240000000L",
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"f_flash": "40000000L",
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"flash_mode": "dio",
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@@ -5,7 +5,7 @@
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"memory_type": "dio_qspi"
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},
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"core": "esp32",
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"extra_flags": "-DARDUINO_ESP32_DEV -DBOARD_HAS_PSRAM -DARDUINO_USB_CDC_ON_BOOT=0 -DESP32_16M",
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"extra_flags": "-DARDUINO_ESP32_DEV -DBOARD_HAS_PSRAM -DARDUINO_USB_CDC_ON_BOOT=0 -DESP32_16M -DESP32_CLASIC",
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"f_cpu": "240000000L",
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"f_flash": "40000000L",
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"flash_mode": "dio",
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@@ -5,7 +5,7 @@
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"memory_type": "dio_qspi"
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},
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"core": "esp32",
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"extra_flags": "-DARDUINO_ESP32_DEV -DBOARD_HAS_PSRAM -DARDUINO_USB_CDC_ON_BOOT=0 -DESP32_4M",
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"extra_flags": "-DARDUINO_ESP32_DEV -DBOARD_HAS_PSRAM -DARDUINO_USB_CDC_ON_BOOT=0 -DESP32_4M -DESP32_CLASIC",
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"f_cpu": "240000000L",
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"f_flash": "40000000L",
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"flash_mode": "dio",
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@@ -5,7 +5,7 @@
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"memory_type": "dio_qspi"
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},
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"core": "esp32",
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"extra_flags": "-DARDUINO_ESP32_DEV -DBOARD_HAS_PSRAM -DHAS_PSRAM_FIX -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw -DARDUINO_USB_CDC_ON_BOOT=0 -DESP32_4M",
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"extra_flags": "-DARDUINO_ESP32_DEV -DBOARD_HAS_PSRAM -DHAS_PSRAM_FIX -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw -DARDUINO_USB_CDC_ON_BOOT=0 -DESP32_4M -DESP32_CLASIC",
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"f_cpu": "240000000L",
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"f_flash": "40000000L",
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"flash_mode": "dio",
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@@ -5,7 +5,7 @@
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"memory_type": "dio_qspi"
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},
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"core": "esp32",
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"extra_flags": "-DARDUINO_ESP32_DEV -DBOARD_HAS_PSRAM -DARDUINO_USB_CDC_ON_BOOT=0 -DESP32_8M",
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"extra_flags": "-DARDUINO_ESP32_DEV -DBOARD_HAS_PSRAM -DARDUINO_USB_CDC_ON_BOOT=0 -DESP32_8M -DESP32_CLASIC",
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"f_cpu": "240000000L",
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"f_flash": "40000000L",
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"flash_mode": "dio",
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@@ -5,7 +5,7 @@
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"memory_type": "dio_qspi"
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},
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"core": "esp32",
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"extra_flags": "-DARDUINO_ESP32_DEV -DARDUINO_USB_CDC_ON_BOOT=0 -DESP32_4M -DCORE32SOLO1",
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"extra_flags": "-DARDUINO_ESP32_DEV -DARDUINO_USB_CDC_ON_BOOT=0 -DESP32_4M -DCORE32SOLO1 -DESP32_CLASIC",
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"f_cpu": "80000000L",
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"f_flash": "40000000L",
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"flash_mode": "dio",
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@@ -30,9 +30,9 @@ bool ESPeasySerialType::getSerialTypePins(ESPEasySerialPort serType, int& rxPin,
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#ifdef ESP32
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case ESPEasySerialPort::serial0: rxPin = ESP32_SER0_RX; txPin = ESP32_SER0_TX; return true;
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case ESPEasySerialPort::serial1: rxPin = ESP32_SER1_RX; txPin = ESP32_SER1_TX; return true;
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# ifndef ESP32S2
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# if HAS_SERIAL2
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case ESPEasySerialPort::serial2: rxPin = ESP32_SER2_RX; txPin = ESP32_SER2_TX; return true;
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# endif // ifndef ESP32S2
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# endif
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#endif // ifdef ESP32
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#ifdef ESP8266
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case ESPEasySerialPort::serial0: rxPin = 3; txPin = 1; return true;
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@@ -67,12 +67,12 @@ ESPEasySerialPort ESPeasySerialType::getSerialType(ESPEasySerialPort typeHint, i
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if ((receivePin == ESP32_SER1_RX) && (transmitPin == ESP32_SER1_TX)) {
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return ESPEasySerialPort::serial1; // UART1
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}
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# ifndef ESP32S2
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# if HAS_SERIAL2
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if ((receivePin == ESP32_SER2_RX) && (transmitPin == ESP32_SER2_TX)) {
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return ESPEasySerialPort::serial2; // UART2
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}
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# endif // ifndef ESP32S2
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# endif
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if ((receivePin >= 0x48) && (receivePin <= 0x57)) {
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return ESPEasySerialPort::sc16is752; // I2C address range of SC16IS752
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@@ -8,13 +8,6 @@
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#ifdef ESP32
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#if defined(ESP32S2) || defined(ESP32C3)
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#define HAS_SERIAL2 0
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#else
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#define HAS_SERIAL2 1
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#endif
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// Temporary work-around for bug in ESP32 code, where the pin matrix is not cleaned up between calling end() and begin()
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// Work-around is to keep track of the last used pins for a serial port,
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// as it is likely that a node will always use the same pins most of the time.
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@@ -40,9 +33,9 @@ bool pinsChanged(ESPEasySerialPort port,
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switch (port) {
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case ESPEasySerialPort::serial0: return receivePin != receivePin0 || transmitPin != transmitPin0;
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case ESPEasySerialPort::serial1: return receivePin != receivePin1 || transmitPin != transmitPin1;
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# ifndef ESP32S2
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# if HAS_SERIAL2
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case ESPEasySerialPort::serial2: return receivePin != receivePin2 || transmitPin != transmitPin2;
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# endif // ifndef ESP32S2
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# endif
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default:
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// No other hardware serial ports
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break;
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@@ -64,13 +57,13 @@ void setPinsCache(ESPEasySerialPort port,
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transmitPin1 = transmitPin;
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break;
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# ifndef ESP32S2
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# if HAS_SERIAL2
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case ESPEasySerialPort::serial2:
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receivePin2 = receivePin;
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transmitPin2 = transmitPin;
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break;
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# endif // ifndef ESP32S2
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# endif
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default:
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// No other hardware serial ports
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break;
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@@ -90,9 +83,9 @@ ESPeasySerial::ESPeasySerial(
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switch (port) {
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case ESPEasySerialPort::serial0:
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case ESPEasySerialPort::serial1:
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# ifndef ESP32S2
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# if HAS_SERIAL2
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case ESPEasySerialPort::serial2:
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# endif // ifndef ESP32S2
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# endif
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_serialtype = port;
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break;
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default:
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@@ -41,19 +41,32 @@
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# include <ESPEasySoftwareSerial.h>
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#endif // ifndef DISABLE_SOFTWARE_SERIAL
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#ifndef HAS_SERIAL2
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#if defined(ESP32S2) || defined(ESP32C3) || defined(ESP8266)
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#define HAS_SERIAL2 0
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# elif defined(ESP32S3)
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#define HAS_SERIAL2 1
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# elif defined(ESP32_CLASSIC)
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#define HAS_SERIAL2 1
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# else
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static_assert(false, "Implement processor architecture");
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#endif
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#endif
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#ifdef ESP32
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# ifndef DISABLE_SC16IS752_Serial
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# ifndef ESP32S2
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# if HAS_SERIAL2
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# define NR_ESPEASY_SERIAL_TYPES 4 // Serial 0, 1, 2, sc16is752
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# else // ifndef ESP32S2
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# else
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# define NR_ESPEASY_SERIAL_TYPES 3 // Serial 0, 1, sc16is752
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# endif // ifndef ESP32S2
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# endif
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# else // ifndef DISABLE_SC16IS752_Serial
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# ifndef ESP32S2
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# if HAS_SERIAL2
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# define NR_ESPEASY_SERIAL_TYPES 3 // Serial 0, 1, 2
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# else // ifndef ESP32S2
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# else
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# define NR_ESPEASY_SERIAL_TYPES 2 // Serial 0, 1
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# endif // ifndef ESP32S2
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# endif
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# endif // ifndef DISABLE_SC16IS752_Serial
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#endif // ifdef ESP32
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#ifdef ESP8266
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+15
-14
@@ -60,6 +60,7 @@ lib_ignore = ${esp32_always.lib_ignore}
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HeatpumpIR
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ESP32 BLE Arduino
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build_flags = ${esp32_base.build_flags}
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-DESP32_CLASSIC
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extra_scripts = ${esp32_base.extra_scripts}
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build_unflags = ${esp32_base.build_unflags}
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-fexceptions
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@@ -73,14 +74,14 @@ board_build.filesystem = littlefs
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[esp32_IRExt]
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extends = esp32_base
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extends = esp32_common
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lib_ignore = ${esp32_always.lib_ignore}
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ESP32_ping
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build_flags = ${esp32_base.build_flags}
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build_flags = ${esp32_common.build_flags}
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-DFEATURE_ARDUINO_OTA=1
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-DPLUGIN_BUILD_NORMAL_IRext
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-DCOLLECTION_USE_RTTTL
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extra_scripts = ${esp32_base.extra_scripts}
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extra_scripts = ${esp32_common.extra_scripts}
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pre:tools/pio/ir_build_check.py
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@@ -113,14 +114,14 @@ board = esp32_16M8M
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board_upload.flash_size = 16MB
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[env:custom_IR_ESP32_4M316k]
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extends = esp32_base
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extends = esp32_common
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board = esp32_4M
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build_flags = ${esp32_base.build_flags}
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build_flags = ${esp32_common.build_flags}
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-DPLUGIN_BUILD_CUSTOM
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-DPLUGIN_BUILD_IR
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lib_ignore = ${esp32_always.lib_ignore}
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ESP32_ping
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extra_scripts = ${esp32_base.extra_scripts}
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extra_scripts = ${esp32_common.extra_scripts}
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pre:tools/pio/pre_custom_esp32_IR.py
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pre:tools/pio/ir_build_check.py
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@@ -269,16 +270,16 @@ build_flags = ${env:custom_ESP32_4M316k.build_flags}
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extra_scripts = ${env:custom_ESP32_4M316k.extra_scripts}
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[env:custom_IR_ESP32_16M8M_LittleFS_ETH]
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extends = esp32_base
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extends = esp32_common
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board = esp32_16M8M
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board_upload.flash_size = 16MB
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build_flags = ${esp32_base.build_flags}
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build_flags = ${esp32_common.build_flags}
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-DPLUGIN_BUILD_CUSTOM
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-DPLUGIN_BUILD_IR
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-DFEATURE_ETHERNET=1
|
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lib_ignore = ${esp32_always.lib_ignore}
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ESP32_ping
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extra_scripts = ${esp32_base.extra_scripts}
|
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extra_scripts = ${esp32_common.extra_scripts}
|
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pre:tools/pio/pre_custom_esp32.py
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pre:tools/pio/ir_build_check.py
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|
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@@ -424,12 +425,12 @@ build_flags = ${env:neopixel_ESP32_4M316k.build_flags}
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||||
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; A Lolin D32 PRO with 16MB Flash, allowing 4MB sketch size, and file storage using the default (SPIFFS) filesystem
|
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[env:max_ESP32_16M1M]
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extends = esp32_base
|
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extends = esp32_common
|
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board = esp32_16M1M
|
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board_upload.flash_size = 16MB
|
||||
lib_ignore = ${esp32_always.lib_ignore}
|
||||
ESP32_ping
|
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build_flags = ${esp32_base.build_flags}
|
||||
build_flags = ${esp32_common.build_flags}
|
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-DFEATURE_ARDUINO_OTA=1
|
||||
-DPLUGIN_BUILD_MAX_ESP32
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-DPLUGIN_BUILD_IR_EXTENDED
|
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@@ -442,17 +443,17 @@ build_flags = ${env:max_ESP32_16M1M.build_flags}
|
||||
|
||||
; A Lolin D32 PRO with 16MB Flash, allowing 4MB sketch size, and file storage using LittleFS filesystem
|
||||
[env:max_ESP32_16M8M_LittleFS]
|
||||
extends = esp32_base
|
||||
extends = esp32_common
|
||||
board = esp32_16M8M
|
||||
board_upload.flash_size = 16MB
|
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lib_ignore = ${esp32_always.lib_ignore}
|
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ESP32_ping
|
||||
build_flags = ${esp32_base.build_flags}
|
||||
build_flags = ${esp32_common.build_flags}
|
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-DUSE_LITTLEFS
|
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-DFEATURE_ARDUINO_OTA=1
|
||||
-DPLUGIN_BUILD_MAX_ESP32
|
||||
-DPLUGIN_BUILD_IR_EXTENDED
|
||||
extra_scripts = ${esp32_base.extra_scripts}
|
||||
extra_scripts = ${esp32_common.extra_scripts}
|
||||
board_build.filesystem = littlefs
|
||||
|
||||
; If you have a board with Ethernet integrated and 16MB Flash, then this configuration could be enabled, it's based on the max_ESP32_16M8M_LittleFS definition
|
||||
|
||||
@@ -94,6 +94,7 @@ lib_ignore = ${esp32_always.lib_ignore}
|
||||
ESP32_ping
|
||||
build_flags = ${esp32_base.build_flags}
|
||||
${debug_pio.build_flags}
|
||||
-DESP32_CLASSIC
|
||||
-DUSE_LITTLEFS
|
||||
-DFEATURE_ARDUINO_OTA=1
|
||||
-DPLUGIN_BUILD_MAX_ESP32
|
||||
|
||||
+16
-11
@@ -79,24 +79,29 @@
|
||||
|
||||
#ifdef ESP32S2
|
||||
#define NODE_TYPE_ID NODE_TYPE_ID_ESP_EASY32S2_STD
|
||||
#include <esp32s2/rom/rtc.h>
|
||||
#elif defined(ESP32S3)
|
||||
#define NODE_TYPE_ID NODE_TYPE_ID_ESP_EASY32S3_STD
|
||||
#include <esp32s3/rom/rtc.h>
|
||||
#elif defined(ESP32C3)
|
||||
#define NODE_TYPE_ID NODE_TYPE_ID_ESP_EASY32C3_STD
|
||||
#else
|
||||
#include <esp32c3/rom/rtc.h>
|
||||
# elif defined(ESP32_CLASSIC)
|
||||
#define NODE_TYPE_ID NODE_TYPE_ID_ESP_EASY32_STD
|
||||
#if ESP_IDF_VERSION_MAJOR > 3
|
||||
#include <esp32/rom/rtc.h>
|
||||
#else
|
||||
#include <rom/rtc.h>
|
||||
#endif
|
||||
# else
|
||||
|
||||
static_assert(false, "Implement processor architecture");
|
||||
|
||||
#endif
|
||||
// #include <WiFi.h>
|
||||
// #include "esp32_ping.h"
|
||||
|
||||
#ifdef ESP32S2
|
||||
#include <esp32s2/rom/rtc.h>
|
||||
#else
|
||||
#if ESP_IDF_VERSION_MAJOR > 3
|
||||
#include <esp32/rom/rtc.h>
|
||||
#else
|
||||
#include <rom/rtc.h>
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
#include <esp_wifi.h> // Needed to call ESP-IDF functions like esp_wifi_....
|
||||
#endif
|
||||
|
||||
|
||||
+19
-11
@@ -8,6 +8,18 @@
|
||||
|
||||
#if defined(ESP32) && !defined(ESP32C3)
|
||||
|
||||
#ifdef ESP32_CLASSIC
|
||||
# define HAS_T0_INPUT 1
|
||||
# define HAS_T10_TO_T14 0
|
||||
# define LAST_TOUCH_INPUT_INDEX 10
|
||||
#endif
|
||||
#if defined(ESP32S2) || defined(ESP32S3)
|
||||
# define HAS_T0_INPUT 0
|
||||
# define HAS_T10_TO_T14 1
|
||||
# define LAST_TOUCH_INPUT_INDEX 15
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
# define PLUGIN_097
|
||||
@@ -32,11 +44,7 @@
|
||||
// Share this bitmap among all instances of this plugin
|
||||
DRAM_ATTR uint32_t p097_pinTouched = 0;
|
||||
DRAM_ATTR uint32_t p097_pinTouchedPrev = 0;
|
||||
#ifdef ESP32S2
|
||||
DRAM_ATTR uint32_t p097_timestamp[15] = { 0 };
|
||||
#else
|
||||
DRAM_ATTR uint32_t p097_timestamp[10] = { 0 };
|
||||
#endif
|
||||
DRAM_ATTR uint32_t p097_timestamp[LAST_TOUCH_INPUT_INDEX] = { 0 };
|
||||
|
||||
boolean Plugin_097(uint8_t function, struct EventStruct *event, String& string)
|
||||
{
|
||||
@@ -192,7 +200,7 @@ void P097_setEventParams(int pin, uint16_t threshold) {
|
||||
|
||||
if (getADC_gpio_info(pin, adc, ch, t)) {
|
||||
switch (t) {
|
||||
#ifndef ESP32S2
|
||||
#if HAS_T0_INPUT
|
||||
case 0: touchAttachInterrupt(T0, P097_got_T0, threshold); break;
|
||||
#endif
|
||||
case 1: touchAttachInterrupt(T1, P097_got_T1, threshold); break;
|
||||
@@ -204,7 +212,7 @@ void P097_setEventParams(int pin, uint16_t threshold) {
|
||||
case 7: touchAttachInterrupt(T7, P097_got_T7, threshold); break;
|
||||
case 8: touchAttachInterrupt(T8, P097_got_T8, threshold); break;
|
||||
case 9: touchAttachInterrupt(T9, P097_got_T9, threshold); break;
|
||||
#ifdef ESP32S2
|
||||
#if HAS_T10_TO_T14
|
||||
/*
|
||||
case 10: touchAttachInterrupt(T10, P097_got_T10, threshold); break;
|
||||
case 11: touchAttachInterrupt(T11, P097_got_T11, threshold); break;
|
||||
@@ -217,7 +225,7 @@ void P097_setEventParams(int pin, uint16_t threshold) {
|
||||
}
|
||||
}
|
||||
|
||||
#ifndef ESP32S2
|
||||
#if HAS_T0_INPUT
|
||||
void P097_got_T0() IRAM_ATTR;
|
||||
#endif
|
||||
void P097_got_T1() IRAM_ATTR;
|
||||
@@ -229,7 +237,7 @@ void P097_got_T6() IRAM_ATTR;
|
||||
void P097_got_T7() IRAM_ATTR;
|
||||
void P097_got_T8() IRAM_ATTR;
|
||||
void P097_got_T9() IRAM_ATTR;
|
||||
#ifdef ESP32S2
|
||||
#if HAS_T10_TO_T14
|
||||
void P097_got_T10() IRAM_ATTR;
|
||||
void P097_got_T11() IRAM_ATTR;
|
||||
void P097_got_T12() IRAM_ATTR;
|
||||
@@ -237,7 +245,7 @@ void P097_got_T13() IRAM_ATTR;
|
||||
void P097_got_T14() IRAM_ATTR;
|
||||
#endif
|
||||
|
||||
#ifndef ESP32S2
|
||||
#if HAS_T0_INPUT
|
||||
void P097_got_T0() {
|
||||
bitSet(p097_pinTouched, 0);
|
||||
|
||||
@@ -299,7 +307,7 @@ void P097_got_T9() {
|
||||
if (p097_timestamp[9] == 0) { p097_timestamp[9] = millis(); }
|
||||
}
|
||||
|
||||
#ifdef ESP32S2
|
||||
#if HAS_T10_TO_T14
|
||||
void P097_got_T10() {
|
||||
bitSet(p097_pinTouched, 10);
|
||||
|
||||
|
||||
@@ -32,10 +32,14 @@
|
||||
#if defined(ESP32)
|
||||
#if defined(ESP32S2)
|
||||
# define BUILD_NOTES " - Mega32-s2"
|
||||
#elif defined(ESP32C2)
|
||||
#elif defined(ESP32S3)
|
||||
# define BUILD_NOTES " - Mega32-s3"
|
||||
#elif defined(ESP32C3)
|
||||
# define BUILD_NOTES " - Mega32-c3"
|
||||
#else
|
||||
# elif defined(ESP32_CLASSIC)
|
||||
# define BUILD_NOTES " - Mega32"
|
||||
# else
|
||||
static_assert(false, "Implement processor architecture");
|
||||
#endif
|
||||
#endif // if defined(ESP32)
|
||||
#endif
|
||||
|
||||
@@ -8,7 +8,9 @@
|
||||
#define NODE_TYPE_ID_ESP_EASYM_STD 17
|
||||
#define NODE_TYPE_ID_ESP_EASY32_STD 33
|
||||
#define NODE_TYPE_ID_ESP_EASY32S2_STD 34
|
||||
#define NODE_TYPE_ID_ESP_EASY32C3_STD 35
|
||||
#define NODE_TYPE_ID_ESP_EASY32S3_STD 35
|
||||
#define NODE_TYPE_ID_ESP_EASY32C2_STD 36
|
||||
#define NODE_TYPE_ID_ESP_EASY32C3_STD 37
|
||||
#define NODE_TYPE_ID_ARDUINO_EASY_STD 65
|
||||
#define NODE_TYPE_ID_NANO_EASY_STD 81
|
||||
|
||||
|
||||
+197
-76
@@ -90,7 +90,7 @@ void hardwareInit()
|
||||
bool hasPullUp, hasPullDown;
|
||||
|
||||
for (int gpio = 0; gpio <= MAX_GPIO; ++gpio) {
|
||||
const bool serialPinConflict = (Settings.UseSerial && (gpio == 1 || gpio == 3));
|
||||
const bool serialPinConflict = isSerialConsolePin(gpio);
|
||||
|
||||
if (!serialPinConflict) {
|
||||
const uint32_t key = createKey(1, gpio);
|
||||
@@ -265,7 +265,7 @@ void initI2C() {
|
||||
#endif // if defined(ESP8266)
|
||||
#ifdef ESP32
|
||||
Wire.setTimeOut(Settings.WireClockStretchLimit);
|
||||
#endif // ifdef ESP32S2
|
||||
#endif
|
||||
}
|
||||
|
||||
#if FEATURE_I2CMULTIPLEXER
|
||||
@@ -1187,41 +1187,104 @@ void readBootCause() {
|
||||
void readBootCause() {
|
||||
lastBootCause = BOOT_CAUSE_MANUAL_REBOOT;
|
||||
|
||||
#ifdef ESP32S2
|
||||
|
||||
switch (rtc_get_reset_reason(0)) {
|
||||
case NO_MEAN: break;
|
||||
case POWERON_RESET: lastBootCause = BOOT_CAUSE_MANUAL_REBOOT; break;
|
||||
# ifndef ESP32S2
|
||||
case SW_RESET: lastBootCause = BOOT_CAUSE_SOFT_RESTART; break;
|
||||
case OWDT_RESET: lastBootCause = BOOT_CAUSE_SW_WATCHDOG; break;
|
||||
# endif // ifndef ESP32S2
|
||||
case DEEPSLEEP_RESET: lastBootCause = BOOT_CAUSE_DEEP_SLEEP; break;
|
||||
# ifndef ESP32S2
|
||||
case SDIO_RESET: lastBootCause = BOOT_CAUSE_MANUAL_REBOOT; break;
|
||||
# endif // ifndef ESP32S2
|
||||
case TG0WDT_SYS_RESET:
|
||||
case TG1WDT_SYS_RESET:
|
||||
case RTCWDT_SYS_RESET: lastBootCause = BOOT_CAUSE_EXT_WD; break;
|
||||
# ifndef ESP32S2
|
||||
case SW_CPU_RESET:
|
||||
case TGWDT_CPU_RESET:
|
||||
# endif // ifndef ESP32S2
|
||||
case INTRUSION_RESET: lastBootCause = BOOT_CAUSE_SOFT_RESTART; break; // Both call to ESP.reset() and on exception crash
|
||||
case RTCWDT_CPU_RESET: lastBootCause = BOOT_CAUSE_EXT_WD; break;
|
||||
# ifndef ESP32S2
|
||||
case EXT_CPU_RESET: lastBootCause = BOOT_CAUSE_MANUAL_REBOOT; break; // reset button or cold boot, only for core 1
|
||||
# endif // ifndef ESP32S2
|
||||
case RTCWDT_BROWN_OUT_RESET: lastBootCause = BOOT_CAUSE_POWER_UNSTABLE; break;
|
||||
case RTCWDT_RTC_RESET: lastBootCause = BOOT_CAUSE_COLD_BOOT; break;
|
||||
# ifdef ESP32S2
|
||||
case RTC_SW_SYS_RESET: lastBootCause = BOOT_CAUSE_SOFT_RESTART; break;
|
||||
case TG0WDT_CPU_RESET: lastBootCause = BOOT_CAUSE_EXT_WD; break;
|
||||
case RTC_SW_CPU_RESET: lastBootCause = BOOT_CAUSE_SOFT_RESTART; break;
|
||||
case TG1WDT_CPU_RESET: lastBootCause = BOOT_CAUSE_EXT_WD; break;
|
||||
case SUPER_WDT_RESET: lastBootCause = BOOT_CAUSE_EXT_WD; break;
|
||||
case GLITCH_RTC_RESET: lastBootCause = BOOT_CAUSE_POWER_UNSTABLE; break; // FIXME TD-er: Does this need a different reason?
|
||||
case EFUSE_RESET: break; // FIXME TD-er: No idea what may cause this reset reason.
|
||||
# endif // ifdef ESP32S2
|
||||
case NO_MEAN : break;
|
||||
case POWERON_RESET : lastBootCause = BOOT_CAUSE_MANUAL_REBOOT; break; /**<1, Vbat power on reset*/
|
||||
case RTC_SW_SYS_RESET : lastBootCause = BOOT_CAUSE_SOFT_RESTART; break; /**<3, Software reset digital core*/
|
||||
case DEEPSLEEP_RESET : lastBootCause = BOOT_CAUSE_DEEP_SLEEP; break; /**<5, Deep Sleep reset digital core*/
|
||||
case TG0WDT_SYS_RESET : lastBootCause = BOOT_CAUSE_EXT_WD; break; /**<7, Timer Group0 Watch dog reset digital core*/
|
||||
case TG1WDT_SYS_RESET : lastBootCause = BOOT_CAUSE_EXT_WD; break; /**<8, Timer Group1 Watch dog reset digital core*/
|
||||
case RTCWDT_SYS_RESET : lastBootCause = BOOT_CAUSE_EXT_WD; break; /**<9, RTC Watch dog Reset digital core*/
|
||||
case INTRUSION_RESET : lastBootCause = BOOT_CAUSE_SOFT_RESTART; break; /**<10, Instrusion tested to reset CPU*/
|
||||
case TG0WDT_CPU_RESET : lastBootCause = BOOT_CAUSE_EXT_WD; break; /**<11, Time Group0 reset CPU*/
|
||||
case RTC_SW_CPU_RESET : lastBootCause = BOOT_CAUSE_SOFT_RESTART; break; /**<12, Software reset CPU*/
|
||||
case RTCWDT_CPU_RESET : lastBootCause = BOOT_CAUSE_EXT_WD; break; /**<13, RTC Watch dog Reset CPU*/
|
||||
case RTCWDT_BROWN_OUT_RESET : lastBootCause = BOOT_CAUSE_POWER_UNSTABLE; break; /**<15, Reset when the vdd voltage is not stable*/
|
||||
case RTCWDT_RTC_RESET : lastBootCause = BOOT_CAUSE_EXT_WD; break; /**<16, RTC Watch dog reset digital core and rtc module*/
|
||||
case TG1WDT_CPU_RESET : lastBootCause = BOOT_CAUSE_EXT_WD; break; /**<17, Time Group1 reset CPU*/
|
||||
case SUPER_WDT_RESET : lastBootCause = BOOT_CAUSE_EXT_WD; break; /**<18, super watchdog reset digital core and rtc module*/
|
||||
case GLITCH_RTC_RESET : lastBootCause = BOOT_CAUSE_POWER_UNSTABLE; break; /**<19, glitch reset digital core and rtc module*/
|
||||
case EFUSE_RESET : lastBootCause = BOOT_CAUSE_MANUAL_REBOOT; break; /**<20, efuse reset digital core*/
|
||||
}
|
||||
|
||||
|
||||
|
||||
#elif defined(ESP32S3)
|
||||
switch (rtc_get_reset_reason(0)) {
|
||||
case NO_MEAN : break;
|
||||
case POWERON_RESET : lastBootCause = BOOT_CAUSE_MANUAL_REBOOT; break; /**<1, Vbat power on reset*/
|
||||
case RTC_SW_SYS_RESET : lastBootCause = BOOT_CAUSE_SOFT_RESTART; break; /**<3, Software reset digital core*/
|
||||
case DEEPSLEEP_RESET : lastBootCause = BOOT_CAUSE_DEEP_SLEEP; break; /**<5, Deep Sleep reset digital core*/
|
||||
case TG0WDT_SYS_RESET : lastBootCause = BOOT_CAUSE_EXT_WD; break; /**<7, Timer Group0 Watch dog reset digital core*/
|
||||
case TG1WDT_SYS_RESET : lastBootCause = BOOT_CAUSE_EXT_WD; break; /**<8, Timer Group1 Watch dog reset digital core*/
|
||||
case RTCWDT_SYS_RESET : lastBootCause = BOOT_CAUSE_EXT_WD; break; /**<9, RTC Watch dog Reset digital core*/
|
||||
case INTRUSION_RESET : lastBootCause = BOOT_CAUSE_SOFT_RESTART; break; /**<10, Instrusion tested to reset CPU*/
|
||||
case TG0WDT_CPU_RESET : lastBootCause = BOOT_CAUSE_EXT_WD; break; /**<11, Time Group0 reset CPU*/
|
||||
case RTC_SW_CPU_RESET : lastBootCause = BOOT_CAUSE_SOFT_RESTART; break; /**<12, Software reset CPU*/
|
||||
case RTCWDT_CPU_RESET : lastBootCause = BOOT_CAUSE_EXT_WD; break; /**<13, RTC Watch dog Reset CPU*/
|
||||
case RTCWDT_BROWN_OUT_RESET : lastBootCause = BOOT_CAUSE_POWER_UNSTABLE; break; /**<15, Reset when the vdd voltage is not stable*/
|
||||
case RTCWDT_RTC_RESET : lastBootCause = BOOT_CAUSE_EXT_WD; break; /**<16, RTC Watch dog reset digital core and rtc module*/
|
||||
case TG1WDT_CPU_RESET : lastBootCause = BOOT_CAUSE_EXT_WD; break; /**<17, Time Group1 reset CPU*/
|
||||
case SUPER_WDT_RESET : lastBootCause = BOOT_CAUSE_EXT_WD; break; /**<18, super watchdog reset digital core and rtc module*/
|
||||
case GLITCH_RTC_RESET : lastBootCause = BOOT_CAUSE_POWER_UNSTABLE; break; /**<19, glitch reset digital core and rtc module*/
|
||||
case EFUSE_RESET : lastBootCause = BOOT_CAUSE_MANUAL_REBOOT; break; /**<20, efuse reset digital core*/
|
||||
case USB_UART_CHIP_RESET : lastBootCause = BOOT_CAUSE_MANUAL_REBOOT; break; /**<21, usb uart reset digital core */
|
||||
case USB_JTAG_CHIP_RESET : lastBootCause = BOOT_CAUSE_MANUAL_REBOOT; break; /**<22, usb jtag reset digital core */
|
||||
case POWER_GLITCH_RESET : lastBootCause = BOOT_CAUSE_POWER_UNSTABLE; break; /**<23, power glitch reset digital core and rtc module*/
|
||||
}
|
||||
|
||||
|
||||
#elif defined(ESP32C3)
|
||||
switch (rtc_get_reset_reason(0)) {
|
||||
case NO_MEAN : break;
|
||||
case POWERON_RESET : lastBootCause = BOOT_CAUSE_MANUAL_REBOOT; break; /**<1, Vbat power on reset*/
|
||||
case RTC_SW_SYS_RESET : lastBootCause = BOOT_CAUSE_SOFT_RESTART; break; /**<3, Software reset digital core*/
|
||||
case DEEPSLEEP_RESET : lastBootCause = BOOT_CAUSE_DEEP_SLEEP; break; /**<5, Deep Sleep reset digital core*/
|
||||
case TG0WDT_SYS_RESET : lastBootCause = BOOT_CAUSE_EXT_WD; break; /**<7, Timer Group0 Watch dog reset digital core*/
|
||||
case TG1WDT_SYS_RESET : lastBootCause = BOOT_CAUSE_EXT_WD; break; /**<8, Timer Group1 Watch dog reset digital core*/
|
||||
case RTCWDT_SYS_RESET : lastBootCause = BOOT_CAUSE_EXT_WD; break; /**<9, RTC Watch dog Reset digital core*/
|
||||
case INTRUSION_RESET : lastBootCause = BOOT_CAUSE_SOFT_RESTART; break; /**<10, Instrusion tested to reset CPU*/
|
||||
case TG0WDT_CPU_RESET : lastBootCause = BOOT_CAUSE_EXT_WD; break; /**<11, Time Group0 reset CPU*/
|
||||
case RTC_SW_CPU_RESET : lastBootCause = BOOT_CAUSE_SOFT_RESTART; break; /**<12, Software reset CPU*/
|
||||
case RTCWDT_CPU_RESET : lastBootCause = BOOT_CAUSE_EXT_WD; break; /**<13, RTC Watch dog Reset CPU*/
|
||||
case RTCWDT_BROWN_OUT_RESET : lastBootCause = BOOT_CAUSE_POWER_UNSTABLE; break; /**<15, Reset when the vdd voltage is not stable*/
|
||||
case RTCWDT_RTC_RESET : lastBootCause = BOOT_CAUSE_EXT_WD; break; /**<16, RTC Watch dog reset digital core and rtc module*/
|
||||
case TG1WDT_CPU_RESET : lastBootCause = BOOT_CAUSE_EXT_WD; break; /**<17, Time Group1 reset CPU*/
|
||||
case SUPER_WDT_RESET : lastBootCause = BOOT_CAUSE_EXT_WD; break; /**<18, super watchdog reset digital core and rtc module*/
|
||||
case GLITCH_RTC_RESET : lastBootCause = BOOT_CAUSE_POWER_UNSTABLE; break; /**<19, glitch reset digital core and rtc module*/
|
||||
case EFUSE_RESET : lastBootCause = BOOT_CAUSE_MANUAL_REBOOT; break; /**<20, efuse reset digital core*/
|
||||
case USB_UART_CHIP_RESET : lastBootCause = BOOT_CAUSE_MANUAL_REBOOT; break; /**<21, usb uart reset digital core */
|
||||
case USB_JTAG_CHIP_RESET : lastBootCause = BOOT_CAUSE_MANUAL_REBOOT; break; /**<22, usb jtag reset digital core */
|
||||
case POWER_GLITCH_RESET : lastBootCause = BOOT_CAUSE_POWER_UNSTABLE; break; /**<23, power glitch reset digital core and rtc module*/
|
||||
}
|
||||
|
||||
# elif defined(ESP32_CLASSIC)
|
||||
switch (rtc_get_reset_reason(0)) {
|
||||
case NO_MEAN : break;
|
||||
case POWERON_RESET : lastBootCause = BOOT_CAUSE_MANUAL_REBOOT; break; /**<1, Vbat power on reset*/
|
||||
case SW_RESET : lastBootCause = BOOT_CAUSE_SOFT_RESTART; break; /**<3, Software reset digital core*/
|
||||
case OWDT_RESET : lastBootCause = BOOT_CAUSE_SW_WATCHDOG; break; /**<4, Legacy watch dog reset digital core*/
|
||||
case DEEPSLEEP_RESET : lastBootCause = BOOT_CAUSE_DEEP_SLEEP; break; /**<3, Deep Sleep reset digital core*/
|
||||
case SDIO_RESET : lastBootCause = BOOT_CAUSE_MANUAL_REBOOT; break; /**<6, Reset by SLC module, reset digital core*/
|
||||
case TG0WDT_SYS_RESET : lastBootCause = BOOT_CAUSE_EXT_WD; break; /**<7, Timer Group0 Watch dog reset digital core*/
|
||||
case TG1WDT_SYS_RESET : lastBootCause = BOOT_CAUSE_EXT_WD; break; /**<8, Timer Group1 Watch dog reset digital core*/
|
||||
case RTCWDT_SYS_RESET : lastBootCause = BOOT_CAUSE_EXT_WD; break; /**<9, RTC Watch dog Reset digital core*/
|
||||
case INTRUSION_RESET : lastBootCause = BOOT_CAUSE_SOFT_RESTART; break; /**<10, Instrusion tested to reset CPU*/
|
||||
case TGWDT_CPU_RESET : lastBootCause = BOOT_CAUSE_EXT_WD; break; /**<11, Time Group reset CPU*/
|
||||
case SW_CPU_RESET : lastBootCause = BOOT_CAUSE_SOFT_RESTART; break; /**<12, Software reset CPU*/
|
||||
case RTCWDT_CPU_RESET : lastBootCause = BOOT_CAUSE_EXT_WD; break; /**<13, RTC Watch dog Reset CPU*/
|
||||
case EXT_CPU_RESET : lastBootCause = BOOT_CAUSE_MANUAL_REBOOT; break; /**<14, for APP CPU, reseted by PRO CPU*/
|
||||
case RTCWDT_BROWN_OUT_RESET : lastBootCause = BOOT_CAUSE_POWER_UNSTABLE; break; /**<15, Reset when the vdd voltage is not stable*/
|
||||
case RTCWDT_RTC_RESET : lastBootCause = BOOT_CAUSE_EXT_WD; break; /**<16, RTC Watch dog reset digital core and rtc module*/
|
||||
}
|
||||
|
||||
# else
|
||||
|
||||
static_assert(false, "Implement processor architecture");
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif // ifdef ESP32
|
||||
@@ -1460,6 +1523,7 @@ bool getGpioInfo(int gpio, int& pinnr, bool& input, bool& output, bool& warning)
|
||||
|
||||
input = GPIO_IS_VALID_GPIO(gpio);
|
||||
output = GPIO_IS_VALID_OUTPUT_GPIO(gpio);
|
||||
warning = false;
|
||||
|
||||
# ifdef ESP32S2
|
||||
|
||||
@@ -1522,8 +1586,8 @@ bool getGpioInfo(int gpio, int& pinnr, bool& input, bool& output, bool& warning)
|
||||
// GPIO33~37 are connected to SPIIO4 ~ SPIIO7 and SPIDQS.
|
||||
// Therefore, on boards embedded with ESP32-S3R8 / ESP32-S3R8V chip,
|
||||
// GPIO33~37 are also not recommended for other uses.
|
||||
input = false;
|
||||
output = false;
|
||||
input = gpio > 32;
|
||||
output = gpio > 32;
|
||||
warning = true;
|
||||
}
|
||||
|
||||
@@ -1549,6 +1613,29 @@ bool getGpioInfo(int gpio, int& pinnr, bool& input, bool& output, bool& warning)
|
||||
// - https://docs.espressif.com/projects/esp-idf/en/latest/esp32c3/api-reference/peripherals/gpio.html
|
||||
// Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf
|
||||
|
||||
if (gpio == 2) {
|
||||
// Strapping pin which must be high during boot
|
||||
warning = true;
|
||||
}
|
||||
|
||||
/*
|
||||
if (gpio == 8) {
|
||||
// Strapping pin which must be high during flashing
|
||||
warning = true;
|
||||
}
|
||||
*/
|
||||
if (gpio == 9) {
|
||||
// Strapping pin to force download mode (like GPIO-0 on ESP8266/ESP32-classic)
|
||||
warning = true;
|
||||
}
|
||||
|
||||
if (gpio == 11) {
|
||||
// By default VDD_SPI is the power supply pin for embedded flash or external flash. It can only be used as GPIO11
|
||||
// only when the chip is connected to an external flash, and this flash is powered by an external power supply
|
||||
input = false;
|
||||
output = false;
|
||||
warning = true;
|
||||
}
|
||||
|
||||
if ((gpio >= 12) && (gpio <= 17)) {
|
||||
// Connected to the integrated SPI flash.
|
||||
@@ -1557,6 +1644,12 @@ bool getGpioInfo(int gpio, int& pinnr, bool& input, bool& output, bool& warning)
|
||||
warning = true;
|
||||
}
|
||||
|
||||
if (gpio == 18 || gpio == 19) {
|
||||
// USB OTG and USB Serial/JTAG function. USB signal is a differential
|
||||
// signal transmitted over a pair of D+ and D- wires.
|
||||
warning = true;
|
||||
}
|
||||
|
||||
|
||||
if ((input == false) && (output == false)) {
|
||||
return false;
|
||||
@@ -1569,7 +1662,7 @@ bool getGpioInfo(int gpio, int& pinnr, bool& input, bool& output, bool& warning)
|
||||
|
||||
|
||||
|
||||
# else
|
||||
# elif defined(ESP32_CLASSIC)
|
||||
|
||||
// ESP32 classic
|
||||
|
||||
@@ -1601,7 +1694,8 @@ bool getGpioInfo(int gpio, int& pinnr, bool& input, bool& output, bool& warning)
|
||||
}
|
||||
|
||||
// GPIO 0 & 2 can't be used as an input. State during boot is dependent on boot mode.
|
||||
warning = (gpio == 0 || gpio == 2);
|
||||
if (gpio == 0 || gpio == 2)
|
||||
warning = true;
|
||||
|
||||
if (gpio == 12) {
|
||||
// If driven High, flash voltage (VDD_SDIO) is 1.8V not default 3.3V.
|
||||
@@ -1654,7 +1748,9 @@ bool getGpioInfo(int gpio, int& pinnr, bool& input, bool& output, bool& warning)
|
||||
}
|
||||
}
|
||||
|
||||
# endif // ifdef ESP32S2
|
||||
# else
|
||||
static_assert(false, "Implement processor architecture");
|
||||
# endif
|
||||
|
||||
return true;
|
||||
}
|
||||
@@ -1674,11 +1770,26 @@ bool getGpioPullResistor(int gpio, bool& hasPullUp, bool& hasPullDown) {
|
||||
|
||||
# ifdef ESP32S2
|
||||
|
||||
// GPI: GPIO46 is fixed to pull-down and is input only.
|
||||
if (gpio <= 45) {
|
||||
hasPullUp = true;
|
||||
hasPullDown = true;
|
||||
}
|
||||
# else // ifdef ESP32S2
|
||||
#elif defined(ESP32S3)
|
||||
|
||||
if (gpio <= MAX_GPIO) {
|
||||
hasPullUp = true;
|
||||
hasPullDown = true;
|
||||
}
|
||||
|
||||
#elif defined(ESP32C3)
|
||||
|
||||
if (gpio <= MAX_GPIO) {
|
||||
hasPullUp = true;
|
||||
hasPullDown = true;
|
||||
}
|
||||
|
||||
# elif defined(ESP32_CLASSIC)
|
||||
|
||||
// ESP32 classic
|
||||
if (gpio >= 34) {
|
||||
@@ -1692,7 +1803,9 @@ bool getGpioPullResistor(int gpio, bool& hasPullUp, bool& hasPullDown) {
|
||||
hasPullDown = true;
|
||||
}
|
||||
|
||||
# endif // ifdef ESP32S2
|
||||
# else
|
||||
static_assert(false, "Implement processor architecture");
|
||||
# endif
|
||||
return true;
|
||||
}
|
||||
|
||||
@@ -1788,6 +1901,34 @@ bool validGpio(int gpio) {
|
||||
return getGpioInfo(gpio, pinnr, input, output, warning);
|
||||
}
|
||||
|
||||
bool isSerialConsolePin(int gpio) {
|
||||
if (!Settings.UseSerial) return false;
|
||||
|
||||
# ifdef ESP32S2
|
||||
// FIXME TD-er: Must check whether USB serial is used
|
||||
return gpio == 1 || gpio == 3;
|
||||
|
||||
#elif defined(ESP32S3)
|
||||
// FIXME TD-er: Must check whether USB serial is used
|
||||
return gpio == 43 || gpio == 44;
|
||||
|
||||
#elif defined(ESP32C3)
|
||||
// FIXME TD-er: Must check whether USB serial is used
|
||||
return gpio == 21 || gpio == 20;
|
||||
|
||||
# elif defined(ESP32_CLASSIC)
|
||||
return gpio == 1 || gpio == 3;
|
||||
|
||||
# elif defined(ESP8266)
|
||||
return gpio == 1 || gpio == 3;
|
||||
|
||||
# else
|
||||
static_assert(false, "Implement processor architecture");
|
||||
return false;
|
||||
# endif
|
||||
|
||||
}
|
||||
|
||||
#ifdef ESP32
|
||||
|
||||
// Get ADC related info for a given GPIO pin
|
||||
@@ -1801,7 +1942,7 @@ bool getADC_gpio_info(int gpio_pin, int& adc, int& ch, int& t)
|
||||
ch = -1;
|
||||
t = -1;
|
||||
|
||||
# ifdef ESP32S2
|
||||
#if defined(ESP32S2) || defined(ESP32S3)
|
||||
|
||||
switch (gpio_pin) {
|
||||
case 1: adc = 1; ch = 0; t = 1; break;
|
||||
@@ -1827,34 +1968,6 @@ bool getADC_gpio_info(int gpio_pin, int& adc, int& ch, int& t)
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
# elif defined(ESP32S3)
|
||||
// FIXME TD-er: Implement for ESP32-S3
|
||||
|
||||
switch (gpio_pin) {
|
||||
case 1: adc = 1; ch = 0; t = 1; break;
|
||||
case 2: adc = 1; ch = 1; t = 2; break;
|
||||
case 3: adc = 1; ch = 2; t = 3; break;
|
||||
case 4: adc = 1; ch = 3; t = 4; break;
|
||||
case 5: adc = 1; ch = 4; t = 5; break;
|
||||
case 6: adc = 1; ch = 5; t = 6; break;
|
||||
case 7: adc = 1; ch = 6; t = 7; break;
|
||||
case 8: adc = 1; ch = 7; t = 8; break;
|
||||
case 9: adc = 1; ch = 8; t = 9; break;
|
||||
case 10: adc = 1; ch = 9; t = 10; break;
|
||||
case 11: adc = 2; ch = 0; t = 11; break;
|
||||
case 12: adc = 2; ch = 1; t = 12; break;
|
||||
case 13: adc = 2; ch = 2; t = 13; break;
|
||||
case 14: adc = 2; ch = 3; t = 14; break;
|
||||
case 15: adc = 2; ch = 4; break;
|
||||
case 16: adc = 2; ch = 5; break;
|
||||
case 17: adc = 2; ch = 6; break;
|
||||
case 18: adc = 2; ch = 7; break;
|
||||
case 19: adc = 2; ch = 8; break;
|
||||
case 20: adc = 2; ch = 9; break;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
|
||||
# elif defined(ESP32C3)
|
||||
@@ -1870,8 +1983,7 @@ bool getADC_gpio_info(int gpio_pin, int& adc, int& ch, int& t)
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
# else
|
||||
# elif defined(ESP32_CLASSIC)
|
||||
|
||||
// Classic ESP32
|
||||
switch (gpio_pin) {
|
||||
@@ -1897,7 +2009,13 @@ bool getADC_gpio_info(int gpio_pin, int& adc, int& ch, int& t)
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
# endif // ifdef ESP32S2
|
||||
|
||||
# else
|
||||
|
||||
static_assert(false, "Implement processor architecture");
|
||||
|
||||
|
||||
# endif
|
||||
return true;
|
||||
}
|
||||
|
||||
@@ -1928,7 +2046,7 @@ int touchPinToGpio(int touch_pin)
|
||||
// No touch pin support
|
||||
|
||||
|
||||
# else
|
||||
# elif defined(ESP32_CLASSIC)
|
||||
// ESP32 classic
|
||||
switch (touch_pin) {
|
||||
case 0: return T0;
|
||||
@@ -1944,7 +2062,10 @@ int touchPinToGpio(int touch_pin)
|
||||
default:
|
||||
break;
|
||||
}
|
||||
# endif // ifdef ESP32S2
|
||||
|
||||
# else
|
||||
static_assert(false, "Implement processor architecture");
|
||||
# endif
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
@@ -218,6 +218,8 @@ bool getGpioPullResistor(int gpio,
|
||||
|
||||
bool validGpio(int gpio);
|
||||
|
||||
bool isSerialConsolePin(int gpio);
|
||||
|
||||
|
||||
#ifdef ESP32
|
||||
|
||||
|
||||
@@ -142,11 +142,98 @@ String createGPIO_label(int gpio, int pinnr, bool input, bool output, bool warni
|
||||
|
||||
const __FlashStringHelper* getConflictingUse(int gpio, PinSelectPurpose purpose)
|
||||
{
|
||||
|
||||
# ifdef ESP32S2
|
||||
|
||||
if (Settings.UseSerial) {
|
||||
if (gpio == 1) { return F("TX0"); }
|
||||
|
||||
if (gpio == 3) { return F("RX0"); }
|
||||
}
|
||||
|
||||
|
||||
if (FoundPSRAM() && (gpio == 26)) {
|
||||
// ESP32-S2 PSRAM can use GPIO 26 (and 27..32 but those are always unavailable)
|
||||
return F("PSRAM");
|
||||
}
|
||||
|
||||
#elif defined(ESP32S3)
|
||||
|
||||
// SPI0/1: GPIO26-32 are usually used for SPI flash and PSRAM and not recommended for other uses.
|
||||
// When using Octal Flash or Octal PSRAM or both, GPIO33~37 are connected to SPIIO4 ~ SPIIO7 and SPIDQS.
|
||||
// Therefore, on boards embedded with ESP32-S3R8 / ESP32-S3R8V chip, GPIO33~37 are also not recommended for other uses.
|
||||
|
||||
if ((gpio >= 26) && (gpio <= 37)) {
|
||||
if (FoundPSRAM()) {
|
||||
return F("PSRAM");
|
||||
} else {
|
||||
return F("Flash");
|
||||
}
|
||||
}
|
||||
|
||||
// See Appendix A, page 71: https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf
|
||||
|
||||
if (gpio == 19) { return F("USB_D-"); }
|
||||
if (gpio == 20) { return F("USB_D+"); }
|
||||
|
||||
if (Settings.UseSerial) {
|
||||
if (gpio == 43) { return F("TX0"); }
|
||||
|
||||
if (gpio == 44) { return F("RX0"); }
|
||||
}
|
||||
|
||||
#elif defined(ESP32C3)
|
||||
|
||||
if (Settings.UseSerial) {
|
||||
if (gpio == 21) { return F("TX0"); }
|
||||
|
||||
if (gpio == 20) { return F("RX0"); }
|
||||
}
|
||||
|
||||
if (gpio == 18) { return F("USB_D-"); }
|
||||
if (gpio == 19) { return F("USB_D+"); }
|
||||
|
||||
if (gpio == 11) {
|
||||
// By default VDD_SPI is the power supply pin for embedded flash or external flash. It can only be used as GPIO11
|
||||
// only when the chip is connected to an external flash, and this flash is powered by an external power supply
|
||||
return F("Flash Vdd");
|
||||
}
|
||||
if ((gpio >= 12) && (gpio <= 17)) {
|
||||
return F("Flash");
|
||||
}
|
||||
|
||||
|
||||
# elif defined(ESP32_CLASSIC)
|
||||
|
||||
if (Settings.UseSerial) {
|
||||
if (gpio == 1) { return F("TX0"); }
|
||||
|
||||
if (gpio == 3) { return F("RX0"); }
|
||||
}
|
||||
|
||||
|
||||
if (FoundPSRAM()) {
|
||||
// ESP32 PSRAM can use GPIO 16 and 17
|
||||
switch (gpio) {
|
||||
case 16:
|
||||
case 17:
|
||||
return F("PSRAM");
|
||||
}
|
||||
}
|
||||
|
||||
# elif defined(ESP8266)
|
||||
|
||||
if (Settings.UseSerial) {
|
||||
if (gpio == 1) { return F("TX0"); }
|
||||
|
||||
if (gpio == 3) { return F("RX0"); }
|
||||
}
|
||||
|
||||
# else
|
||||
static_assert(false, "Implement processor architecture");
|
||||
|
||||
# endif
|
||||
|
||||
bool includeI2C = true;
|
||||
bool includeSPI = true;
|
||||
|
||||
@@ -200,25 +287,7 @@ const __FlashStringHelper* getConflictingUse(int gpio, PinSelectPurpose purpose)
|
||||
}
|
||||
#endif // if FEATURE_ETHERNET
|
||||
|
||||
#ifdef ESP32
|
||||
# ifdef ESP32S2
|
||||
|
||||
if (FoundPSRAM() && (gpio == 26)) {
|
||||
// ESP32-S2 PSRAM can use GPIO 26 (and 27..32 but those are always unavailable)
|
||||
return F("PSRAM");
|
||||
}
|
||||
# else // ifdef ESP32S2
|
||||
|
||||
if (FoundPSRAM()) {
|
||||
// ESP32 PSRAM can use GPIO 16 and 17
|
||||
switch (gpio) {
|
||||
case 16:
|
||||
case 17:
|
||||
return F("PSRAM");
|
||||
}
|
||||
}
|
||||
# endif // ifdef ESP32S2
|
||||
#endif // ifdef ESP32
|
||||
|
||||
return F("");
|
||||
}
|
||||
|
||||
@@ -52,12 +52,6 @@ const __FlashStringHelper * getLastBootCauseString() {
|
||||
}
|
||||
|
||||
#ifdef ESP32
|
||||
#ifdef ESP32S2
|
||||
#include <esp32s2/rom/rtc.h>
|
||||
#else
|
||||
#include <rom/rtc.h>
|
||||
#endif
|
||||
|
||||
|
||||
// See https://github.com/espressif/esp-idf/blob/master/components/esp32/include/rom/rtc.h
|
||||
const __FlashStringHelper * getResetReasonString_f(uint8_t icore, bool& isDEEPSLEEP_RESET) {
|
||||
@@ -65,49 +59,105 @@ const __FlashStringHelper * getResetReasonString_f(uint8_t icore, bool& isDEEPSL
|
||||
|
||||
#ifdef ESP32S2
|
||||
|
||||
// See tools\sdk\esp32\include\esp_rom\include\esp32s2\rom\rtc.h
|
||||
// See tools\sdk\esp32\include\esp_rom\include\esp32s2\rom\rtc.h
|
||||
switch (rtc_get_reset_reason(icore)) {
|
||||
case POWERON_RESET: return F("Vbat power on reset"); // 1
|
||||
case RTC_SW_SYS_RESET: return F("Software reset digital core"); // 3
|
||||
case DEEPSLEEP_RESET: isDEEPSLEEP_RESET = true; break; // 5
|
||||
case TG0WDT_SYS_RESET: return F("Timer Group0 Watch dog reset digital core"); // 7
|
||||
case TG1WDT_SYS_RESET: return F("Timer Group1 Watch dog reset digital core"); // 8
|
||||
case RTCWDT_SYS_RESET: return F("RTC Watch dog Reset digital core"); // 9
|
||||
case INTRUSION_RESET: return F("Instrusion tested to reset CPU"); // 10
|
||||
case TG0WDT_CPU_RESET: return F("Time Group0 reset CPU"); // 11
|
||||
case RTC_SW_CPU_RESET: return F("Software reset CPU"); // 12
|
||||
case RTCWDT_CPU_RESET: return F("RTC Watch dog Reset CPU"); // 13
|
||||
case RTCWDT_BROWN_OUT_RESET: return F("Reset when the vdd voltage is not stable"); // 15
|
||||
case RTCWDT_RTC_RESET: return F("RTC Watch dog reset digital core and rtc module"); // 16
|
||||
case TG1WDT_CPU_RESET: return F("Time Group1 reset CPU"); // 17
|
||||
case SUPER_WDT_RESET: return F("Super watchdog reset digital core and rtc module"); // 18
|
||||
case GLITCH_RTC_RESET: return F("Glitch reset digital core and rtc module"); // 19
|
||||
case EFUSE_RESET: return F("EFUSE_RESET"); // FIXME TD-er: No idea what may cause this
|
||||
case NO_MEAN: break; // Undefined, "No Meaning"
|
||||
case NO_MEAN : break;
|
||||
case POWERON_RESET : return F("Vbat power on reset");
|
||||
case RTC_SW_SYS_RESET : return F("Software reset digital core");
|
||||
case DEEPSLEEP_RESET : isDEEPSLEEP_RESET = true; break;
|
||||
case TG0WDT_SYS_RESET : return F("Timer Group0 Watch dog reset digital core");
|
||||
case TG1WDT_SYS_RESET : return F("Timer Group1 Watch dog reset digital core");
|
||||
case RTCWDT_SYS_RESET : return F("RTC Watch dog Reset digital core");
|
||||
case INTRUSION_RESET : return F("Instrusion tested to reset CPU");
|
||||
case TG0WDT_CPU_RESET : return F("Time Group0 reset CPU");
|
||||
case RTC_SW_CPU_RESET : return F("Software reset CPU");
|
||||
case RTCWDT_CPU_RESET : return F("RTC Watch dog Reset CPU");
|
||||
case RTCWDT_BROWN_OUT_RESET : return F("Reset when the vdd voltage is not stable");
|
||||
case RTCWDT_RTC_RESET : return F("RTC Watch dog reset digital core and rtc module");
|
||||
case TG1WDT_CPU_RESET : return F("Time Group1 reset CPU");
|
||||
case SUPER_WDT_RESET : return F("super watchdog reset digital core and rtc module");
|
||||
case GLITCH_RTC_RESET : return F("glitch reset digital core and rtc module");
|
||||
case EFUSE_RESET : return F("efuse reset digital core");
|
||||
}
|
||||
|
||||
#else
|
||||
#elif defined(ESP32S3)
|
||||
|
||||
// See tools\sdk\esp32\include\esp_rom\include\esp32s3\rom\rtc.h
|
||||
switch (rtc_get_reset_reason(icore)) {
|
||||
case NO_MEAN : break;
|
||||
case POWERON_RESET : return F("Vbat power on reset");
|
||||
case RTC_SW_SYS_RESET : return F("Software reset digital core");
|
||||
case DEEPSLEEP_RESET : isDEEPSLEEP_RESET = true; break;
|
||||
case TG0WDT_SYS_RESET : return F("Timer Group0 Watch dog reset digital core");
|
||||
case TG1WDT_SYS_RESET : return F("Timer Group1 Watch dog reset digital core");
|
||||
case RTCWDT_SYS_RESET : return F("RTC Watch dog Reset digital core");
|
||||
case INTRUSION_RESET : return F("Instrusion tested to reset CPU");
|
||||
case TG0WDT_CPU_RESET : return F("Time Group0 reset CPU");
|
||||
case RTC_SW_CPU_RESET : return F("Software reset CPU");
|
||||
case RTCWDT_CPU_RESET : return F("RTC Watch dog Reset CPU");
|
||||
case RTCWDT_BROWN_OUT_RESET : return F("Reset when the vdd voltage is not stable");
|
||||
case RTCWDT_RTC_RESET : return F("RTC Watch dog reset digital core and rtc module");
|
||||
case TG1WDT_CPU_RESET : return F("Time Group1 reset CPU");
|
||||
case SUPER_WDT_RESET : return F("super watchdog reset digital core and rtc module");
|
||||
case GLITCH_RTC_RESET : return F("glitch reset digital core and rtc module");
|
||||
case EFUSE_RESET : return F("efuse reset digital core");
|
||||
case USB_UART_CHIP_RESET : return F("usb uart reset digital core ");
|
||||
case USB_JTAG_CHIP_RESET : return F("usb jtag reset digital core ");
|
||||
case POWER_GLITCH_RESET : return F("power glitch reset digital core and rtc module");
|
||||
}
|
||||
|
||||
#elif defined(ESP32C3)
|
||||
|
||||
// See tools\sdk\esp32\include\esp_rom\include\esp32c3\rom\rtc.h
|
||||
switch (rtc_get_reset_reason(icore)) {
|
||||
case NO_MEAN : break;
|
||||
case POWERON_RESET : return F("Vbat power on reset");
|
||||
case RTC_SW_SYS_RESET : return F("Software reset digital core");
|
||||
case DEEPSLEEP_RESET : isDEEPSLEEP_RESET = true; break;
|
||||
case TG0WDT_SYS_RESET : return F("Timer Group0 Watch dog reset digital core");
|
||||
case TG1WDT_SYS_RESET : return F("Timer Group1 Watch dog reset digital core");
|
||||
case RTCWDT_SYS_RESET : return F("RTC Watch dog Reset digital core");
|
||||
case INTRUSION_RESET : return F("Instrusion tested to reset CPU");
|
||||
case TG0WDT_CPU_RESET : return F("Time Group0 reset CPU");
|
||||
case RTC_SW_CPU_RESET : return F("Software reset CPU");
|
||||
case RTCWDT_CPU_RESET : return F("RTC Watch dog Reset CPU");
|
||||
case RTCWDT_BROWN_OUT_RESET : return F("Reset when the vdd voltage is not stable");
|
||||
case RTCWDT_RTC_RESET : return F("RTC Watch dog reset digital core and rtc module");
|
||||
case TG1WDT_CPU_RESET : return F("Time Group1 reset CPU");
|
||||
case SUPER_WDT_RESET : return F("super watchdog reset digital core and rtc module");
|
||||
case GLITCH_RTC_RESET : return F("glitch reset digital core and rtc module");
|
||||
case EFUSE_RESET : return F("efuse reset digital core");
|
||||
case USB_UART_CHIP_RESET : return F("usb uart reset digital core ");
|
||||
case USB_JTAG_CHIP_RESET : return F("usb jtag reset digital core ");
|
||||
case POWER_GLITCH_RESET : return F("power glitch reset digital core and rtc module");
|
||||
}
|
||||
|
||||
# elif defined(ESP32_CLASSIC)
|
||||
|
||||
// See https://github.com/espressif/esp-idf/blob/master/components/esp32/include/rom/rtc.h
|
||||
switch (rtc_get_reset_reason((RESET_REASON)icore)) {
|
||||
case NO_MEAN: return F("NO_MEAN");
|
||||
case POWERON_RESET: return F("Vbat power on reset");
|
||||
case SW_RESET: return F("Software reset digital core");
|
||||
case OWDT_RESET: return F("Legacy watch dog reset digital core");
|
||||
case DEEPSLEEP_RESET: isDEEPSLEEP_RESET = true; break;
|
||||
case SDIO_RESET: return F("Reset by SLC module, reset digital core");
|
||||
case TG0WDT_SYS_RESET: return F("Timer Group0 Watch dog reset digital core");
|
||||
case TG1WDT_SYS_RESET: return F("Timer Group1 Watch dog reset digital core");
|
||||
case RTCWDT_SYS_RESET: return F("RTC Watch dog Reset digital core");
|
||||
case INTRUSION_RESET: return F("Instrusion tested to reset CPU");
|
||||
case TGWDT_CPU_RESET: return F("Time Group reset CPU");
|
||||
case SW_CPU_RESET: return F("Software reset CPU");
|
||||
case RTCWDT_CPU_RESET: return F("RTC Watch dog Reset CPU");
|
||||
case EXT_CPU_RESET: return F("for APP CPU, reseted by PRO CPU");
|
||||
case RTCWDT_BROWN_OUT_RESET: return F("Reset when the vdd voltage is not stable");
|
||||
case RTCWDT_RTC_RESET: return F("RTC Watch dog reset digital core and rtc module");
|
||||
case NO_MEAN : break;
|
||||
case POWERON_RESET : return F("Vbat power on reset");
|
||||
case SW_RESET : return F("Software reset digital core");
|
||||
case OWDT_RESET : return F("Legacy watch dog reset digital core");
|
||||
case DEEPSLEEP_RESET : isDEEPSLEEP_RESET = true; break;
|
||||
case SDIO_RESET : return F("Reset by SLC module, reset digital core");
|
||||
case TG0WDT_SYS_RESET : return F("Timer Group0 Watch dog reset digital core");
|
||||
case TG1WDT_SYS_RESET : return F("Timer Group1 Watch dog reset digital core");
|
||||
case RTCWDT_SYS_RESET : return F("RTC Watch dog Reset digital core");
|
||||
case INTRUSION_RESET : return F("Instrusion tested to reset CPU");
|
||||
case TGWDT_CPU_RESET : return F("Time Group reset CPU");
|
||||
case SW_CPU_RESET : return F("Software reset CPU");
|
||||
case RTCWDT_CPU_RESET : return F("RTC Watch dog Reset CPU");
|
||||
case EXT_CPU_RESET : return F("for APP CPU, reseted by PRO CPU");
|
||||
case RTCWDT_BROWN_OUT_RESET : return F("Reset when the vdd voltage is not stable");
|
||||
case RTCWDT_RTC_RESET : return F("RTC Watch dog reset digital core and rtc module");
|
||||
default: break;
|
||||
}
|
||||
|
||||
# else
|
||||
static_assert(false, "Implement processor architecture");
|
||||
|
||||
#endif
|
||||
return F("");
|
||||
}
|
||||
|
||||
@@ -14,6 +14,17 @@
|
||||
|
||||
#include <ESPEasySerialType.h>
|
||||
|
||||
#ifndef HAS_SERIAL2
|
||||
#if defined(ESP32S2) || defined(ESP32C3) || defined(ESP8266)
|
||||
#define HAS_SERIAL2 0
|
||||
# elif defined(ESP32S3)
|
||||
#define HAS_SERIAL2 1
|
||||
# elif defined(ESP32_CLASSIC)
|
||||
#define HAS_SERIAL2 1
|
||||
# else
|
||||
static_assert(false, "Implement processor architecture");
|
||||
#endif
|
||||
#endif
|
||||
|
||||
String serialHelper_getSerialTypeLabel(ESPEasySerialPort serType) {
|
||||
return ESPEasySerialPort_toString(serType);
|
||||
@@ -48,7 +59,7 @@ String serialHelper_getGpioDescription(ESPEasySerialPort typeHint, int config_pi
|
||||
case ESPEasySerialPort::serial0_swap:
|
||||
case ESPEasySerialPort::serial0:
|
||||
case ESPEasySerialPort::serial1:
|
||||
#ifndef ESP32S2
|
||||
#if HAS_SERIAL2
|
||||
case ESPEasySerialPort::serial2:
|
||||
#endif
|
||||
{
|
||||
@@ -227,7 +238,7 @@ void serialHelper_webformLoad(ESPEasySerialPort port, int rxPinDef, int txPinDef
|
||||
case ESPEasySerialPort::serial0:
|
||||
case ESPEasySerialPort::serial0_swap:
|
||||
case ESPEasySerialPort::serial1:
|
||||
#ifndef ESP32S2
|
||||
#if HAS_SERIAL2
|
||||
case ESPEasySerialPort::serial2:
|
||||
#endif
|
||||
{
|
||||
@@ -296,7 +307,7 @@ void serialHelper_webformSave(uint8_t& port, int8_t& rxPin, int8_t& txPin) {
|
||||
case ESPEasySerialPort::serial0:
|
||||
case ESPEasySerialPort::serial0_swap:
|
||||
case ESPEasySerialPort::serial1:
|
||||
#ifndef ESP32S2
|
||||
#if HAS_SERIAL2
|
||||
case ESPEasySerialPort::serial2:
|
||||
#endif
|
||||
{
|
||||
|
||||
@@ -81,7 +81,7 @@ void handle_hardware() {
|
||||
int gpio = 0;
|
||||
|
||||
while (gpio <= MAX_GPIO) {
|
||||
if (Settings.UseSerial && ((gpio == 1) || (gpio == 3))) {
|
||||
if (isSerialConsolePin(gpio)) {
|
||||
// do not add the pin state select for these pins.
|
||||
} else {
|
||||
if (validGpio(gpio)) {
|
||||
|
||||
@@ -330,7 +330,7 @@ void addPinSelector_Item(PinSelectPurpose purpose, const String& gpio_label, int
|
||||
disabled = true;
|
||||
}
|
||||
|
||||
if (Settings.UseSerial && ((gpio == 1) || (gpio == 3))) {
|
||||
if (isSerialConsolePin(gpio)) {
|
||||
disabled = true;
|
||||
}
|
||||
|
||||
|
||||
@@ -643,7 +643,7 @@ void addFormPinStateSelect(int gpio, int choice)
|
||||
{
|
||||
bool enabled = true;
|
||||
|
||||
if (Settings.UseSerial && ((gpio == 1) || (gpio == 3))) {
|
||||
if (isSerialConsolePin(gpio)) {
|
||||
// do not add the pin state select for these pins.
|
||||
enabled = false;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user