[PlatformIO] Fix upload size for 16M boards, causing bootloops

Also got rid of some warnings about unhandled boot causes for ESP32-S2

Set the CPU frequency for "solo" boards to 80MHz

boards/esp32_16M1M.json

@@ -29,7 +29,7 @@
   "upload": {
     "flash_size": "16MB",
     "maximum_ram_size": 327680,
-    "maximum_size": 4194304,
+    "maximum_size": 16777216,
     "require_upload_port": true,
     "speed": 460800
   },

boards/esp32_16M8M.json

@@ -29,7 +29,7 @@
   "upload": {
     "flash_size": "16MB",
     "maximum_ram_size": 327680,
-    "maximum_size": 4194304,
+    "maximum_size": 16777216,
     "require_upload_port": true,
     "speed": 460800
   },

boards/esp32_solo1_4M.json

@@ -5,7 +5,7 @@
     },
     "core": "esp32",
     "extra_flags": "-DARDUINO_ESP32_DEV -DARDUINO_USB_CDC_ON_BOOT=0 -DESP32_4M -DCORE32SOLO1",
-    "f_cpu": "240000000L",
+    "f_cpu": "80000000L",
     "f_flash": "40000000L",
     "flash_mode": "dout",
     "mcu": "esp32",
@@ -29,7 +29,7 @@
   "upload": {
     "flash_size": "4MB",
     "maximum_ram_size": 327680,
-    "maximum_size": 1900544,
+    "maximum_size": 4194304,
     "require_upload_port": true,
     "speed": 460800
   },

platformio_special_envs.ini

@@ -82,7 +82,6 @@ check_flags               = ${debug_pio.check_flags}
 platform                  = ${esp32_common.platform}
 build_flags               = ${esp32_common.build_flags} ${debug_pio.build_flags}   -DPLUGIN_BUILD_CUSTOM
 board                     = esp32_16M8M
-board_upload.maximum_size = 4194304
 extra_scripts             = ${esp32_common.extra_scripts}
                             pre:tools/pio/pre_custom_esp32.py
 
@@ -93,7 +92,6 @@ check_tool                = ${debug_pio.check_tool}
 check_flags               = ${debug_pio.check_flags}
 lib_ignore                = ${esp32_always.lib_ignore}
                             ESP32_ping
-board_upload.maximum_size = 4194304
 build_flags               = ${esp32_base.build_flags}
                             ${debug_pio.build_flags}
                             -DUSE_LITTLEFS

src/src/Helpers/Hardware.cpp

@@ -954,9 +954,7 @@ void readBootCause() {
     #endif
     case TG0WDT_SYS_RESET: 
     case TG1WDT_SYS_RESET:
-    #ifndef ESP32S2
     case RTCWDT_SYS_RESET:  lastBootCause = BOOT_CAUSE_EXT_WD; break;
-    #endif
     #ifndef ESP32S2
     case SW_CPU_RESET:
     case TGWDT_CPU_RESET:
@@ -968,6 +966,14 @@ void readBootCause() {
     #endif
     case RTCWDT_BROWN_OUT_RESET: lastBootCause = BOOT_CAUSE_POWER_UNSTABLE; break;
     case RTCWDT_RTC_RESET:  lastBootCause = BOOT_CAUSE_COLD_BOOT; break;
+    #ifdef ESP32S2
+    case RTC_SW_SYS_RESET: lastBootCause = BOOT_CAUSE_SOFT_RESTART; break;
+    case TG0WDT_CPU_RESET: lastBootCause = BOOT_CAUSE_EXT_WD; break;
+    case RTC_SW_CPU_RESET: lastBootCause = BOOT_CAUSE_SOFT_RESTART; break;
+    case TG1WDT_CPU_RESET: lastBootCause = BOOT_CAUSE_EXT_WD; break;
+    case SUPER_WDT_RESET:   lastBootCause = BOOT_CAUSE_EXT_WD; break;
+    case GLITCH_RTC_RESET:  lastBootCause = BOOT_CAUSE_POWER_UNSTABLE; break; // FIXME TD-er: Does this need a different reason?
+    #endif
   }
 }
 #endif

src/src/Helpers/StringGenerator_System.cpp

@@ -82,6 +82,7 @@ const __FlashStringHelper * getResetReasonString_f(uint8_t icore, bool& isDEEPSL
     case TG1WDT_CPU_RESET:       return F("Time Group1 reset CPU");                            // 17
     case SUPER_WDT_RESET:        return F("Super watchdog reset digital core and rtc module"); // 18
     case GLITCH_RTC_RESET:       return F("Glitch reset digital core and rtc module");         // 19
+    case NO_MEAN:                break; // Undefined, "No Meaning"
   }
 
   #else