Overclock at runtime instead of at start to help stability on marginal boards

sw/CMakeLists.txt

@@ -57,18 +57,10 @@ endfunction()
 
 # Global definitions across all targets
 add_compile_definitions(
-    # 370MHz is extremely closely evenly divisible by 44100Hz
+    # 370MHz is extremely closely evenly divisible by 44100Hz.
+    # Actual overclock happens at runtime via overclock_370mhz() since 370MHz
+    # requires PLL REFDIV=2 which can't be set via SDK boot-time defaults.
     RP2_CLOCK_SPEED=370000
-    SYS_CLK_HZ=370000000
-    # Manually set up PLLs because of non-default REFDIV
-    PLL_SYS_REFDIV=2
-    PLL_SYS_VCO_FREQ_HZ=1110000000
-    PLL_SYS_POSTDIV1=3
-    PLL_SYS_POSTDIV2=1
-    # Set voltage before main so no need to do so on the fly
-    SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST=1
-    SYS_CLK_VREG_VOLTAGE_MIN=VREG_VOLTAGE_1_25
-    SYS_CLK_VREG_VOLTAGE_AUTO_ADJUST_DELAY_US=10000
     PICO_DEFAULT_UART=0
     PICO_DEFAULT_UART_TX_PIN=28
     PICO_DEFAULT_UART_RX_PIN=-1

sw/gusplay.cpp

@@ -74,7 +74,7 @@ static void init_audio(void) {
 
 // Setup values for audio sample clock
 // 8390 clock cycles per sample (370MHz / 8390 ~= 44100Hz)
-static constexpr uint32_t clocks_per_sample_minus_one = (SYS_CLK_HZ / 44100) - 1;
+static constexpr uint32_t clocks_per_sample_minus_one = (RP2_CLOCK_SPEED * 1000u / 44100) - 1;
 static constexpr uint pwm_slice_num = 4; // slices 0-3 are taken by USB joystick support
 
 void audio_sample_handler(void) {

sw/picogus.cpp

@@ -27,6 +27,7 @@
 #include "hardware/vreg.h"
 #include "hardware/clocks.h"
 
+#include "system/overclock.h"
 #include "system/pico_reflash.h"
 #include "system/flash_settings.h"
 
@@ -1207,7 +1208,7 @@ __force_inline bool ior_has_data() {
 }
 
 #if AUDIO_CALLBACK_CORE0
-static constexpr uint32_t clocks_per_sample_minus_one = (SYS_CLK_HZ / 44100) - 1;
+static constexpr uint32_t clocks_per_sample_minus_one = (RP2_CLOCK_SPEED * 1000u / 44100) - 1;
 static constexpr uint pwm_slice_num = 4; // slices 0-3 are taken by USB joystick support
 #endif
 
@@ -1215,6 +1216,7 @@ static constexpr uint pwm_slice_num = 4; // slices 0-3 are taken by USB joystick
 int main()
 {
     busy_wait_ms(250);
+    overclock_370mhz();
 #ifdef ASYNC_UART
     stdio_async_uart_init_full(UART_ID, BAUD_RATE, UART_TX_PIN, UART_RX_PIN);
 #else

sw/sbplay.cpp

@@ -160,7 +160,7 @@ static StereoResampler<get_opl_stereo_sample> opl_resampler;
 
 // Setup values for audio sample clock
 // 8390 clock cycles per sample (370MHz / 8390 ~= 44100Hz)
-static constexpr uint32_t clocks_per_sample_minus_one = (SYS_CLK_HZ / 44100) - 1;
+static constexpr uint32_t clocks_per_sample_minus_one = (RP2_CLOCK_SPEED * 1000u / 44100) - 1;
 static constexpr uint pwm_slice_num = 4; // slices 0-3 are taken by USB joystick support
 
 // Max OPL samples to generate per main-loop iteration.

sw/system/flash_settings.c

@@ -20,6 +20,7 @@
 #include <stdio.h>
 
 #include "flash_settings.h"
+#include "overclock.h"
 #include "hardware/flash.h"
 #include "hardware/sync.h"
 #include "hardware/clocks.h"
@@ -211,8 +212,8 @@ void saveSettings(const Settings* settings)
     flash_range_erase(SETTINGS_SECTOR, FLASH_SECTOR_SIZE);    // last sector
     putchar('/');
     flash_range_program(SETTINGS_SECTOR, data, FLASH_PAGE_SIZE);
-    set_sys_clock_khz(RP2_CLOCK_SPEED, true);
     restore_interrupts(ints);
+    overclock_370mhz();
     printf("settings saved");
 }
 

sw/system/overclock.h

@@ -0,0 +1,67 @@
+/*
+ *  Copyright (C) 2022-2024  Ian Scott
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+#pragma once
+
+#include "hardware/clocks.h"
+#include "hardware/pll.h"
+#include "hardware/timer.h"
+#include "hardware/vreg.h"
+
+// 370MHz PLL configuration:
+// 12MHz XOSC / 2 (REFDIV) = 6MHz reference
+// 6MHz * 185 (FBDIV) = 1110MHz VCO
+// 1110MHz / 3 (POSTDIV1) / 1 (POSTDIV2) = 370MHz
+//
+// 370MHz is extremely closely evenly divisible by 44100Hz, making it ideal for
+// audio sample rate generation. This frequency cannot be achieved with the
+// default REFDIV of 1 since 370 is not evenly divisible by 12.
+static inline void overclock_370mhz(void) {
+    // Bump voltage for stability at 370MHz
+    if (vreg_get_voltage() < VREG_VOLTAGE_1_25) {
+        vreg_set_voltage(VREG_VOLTAGE_1_25);
+        busy_wait_us_32(10000);  // 10ms for voltage to settle
+    }
+
+    // Switch clk_sys to USB PLL (48MHz) while reconfiguring PLL_SYS
+    clock_configure_undivided(clk_sys,
+                    CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX,
+                    CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB,
+                    USB_CLK_HZ);
+
+    // Init PLL_SYS with REFDIV=2 for 370MHz
+    pll_init(pll_sys, 2, 1110000000u, 3, 1);
+
+    // Configure clk_ref to XOSC
+    clock_configure_undivided(clk_ref,
+                    CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC,
+                    0,
+                    XOSC_HZ);
+
+    // Switch clk_sys to PLL_SYS at 370MHz
+    clock_configure_undivided(clk_sys,
+                    CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX,
+                    CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS,
+                    370000000u);
+
+    // Peripheral clock stays on USB PLL (48MHz)
+    clock_configure_undivided(clk_peri,
+                    0,
+                    CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB,
+                    USB_CLK_HZ);
+}