mirror of
https://github.com/olikraus/u8g2.git
synced 2026-07-27 20:05:57 +00:00
fix flipmode
This commit is contained in:
Ikitrusa
+224
-246
@@ -1,268 +1,246 @@
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/*
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u8x8_d_ssd1362z.c
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Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)
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u8x8_d_ssd1362z.c
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Copyright (c) 2022, olikraus@gmail.com
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All rights reserved.
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Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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Copyright (c) 2022, olikraus@gmail.com
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All rights reserved.
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* Redistributions of source code must retain the above copyright notice, this list
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of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright notice, this
|
||||
list of conditions and the following disclaimer in the documentation and/or other
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||||
materials provided with the distribution.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
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CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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||||
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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||||
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* Redistributions of source code must retain the above copyright notice, this list
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of conditions and the following disclaimer.
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PMOLED TRULY OEL1M0033-W-E:
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SSD1362Z:
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256 x 64
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4bit gray scale
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* Redistributions in binary form must reproduce the above copyright notice, this
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list of conditions and the following disclaimer in the documentation and/or other
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materials provided with the distribution.
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Note: Currently the internal IREF is activated.
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Without external VP capacitor
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
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CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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PMOLED TRULY OEL1M0033-W-E:
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SSD1362Z:
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256 x 64
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4bit gray scale
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Note: Currently the internal IREF is activated.
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Without external VP capacitor
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*/
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#include "u8x8.h"
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static const uint8_t u8x8_d_ssd1362z_powersave0_seq[] = {
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U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
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U8X8_C(0x0af), /* ssd1362z: display on */
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U8X8_END_TRANSFER(), /* disable chip */
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U8X8_END() /* end of sequence */
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};
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static const uint8_t u8x8_d_ssd1362z_powersave1_seq[] = {
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U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
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U8X8_C(0x0ae), /* ssd1362z: display off */
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U8X8_END_TRANSFER(), /* disable chip */
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U8X8_END() /* end of sequence */
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};
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/*
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input:
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one tile (8 Bytes)
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output:
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Tile for SSD1362Z (32 Bytes)
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*/
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static uint8_t u8x8_ssd1362z_oel1m0033we_to32_dest_buf[32];
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static uint8_t *u8x8_ssd1362z_oel1m0033we_8to32(U8X8_UNUSED u8x8_t *u8x8, uint8_t *ptr)
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static const uint8_t u8x8_d_ssd1362z_powersave0_seq[] =
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{
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uint8_t v;
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uint8_t a,b;
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uint8_t i, j;
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uint8_t *dest;
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for( j = 0; j < 4; j++ )
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{
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dest = u8x8_ssd1362z_oel1m0033we_to32_dest_buf;
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dest += j;
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a =*ptr;
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ptr++;
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b = *ptr;
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ptr++;
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for( i = 0; i < 8; i++ )
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{
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v = 0;
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if ( a&1 ) v |= 0xf0;
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if ( b&1 ) v |= 0x0f;
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*dest = v;
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dest+=4;
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a >>= 1;
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b >>= 1;
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}
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}
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return u8x8_ssd1362z_oel1m0033we_to32_dest_buf;
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}
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uint8_t u8x8_d_ssd1362z_common(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)
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{
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uint8_t x;
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uint8_t y, c;
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uint8_t *ptr;
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switch(msg)
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{
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/* U8X8_MSG_DISPLAY_SETUP_MEMORY is handled by the calling function */
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/*
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case U8X8_MSG_DISPLAY_SETUP_MEMORY:
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break;
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case U8X8_MSG_DISPLAY_INIT:
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u8x8_d_helper_display_init(u8x8);
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u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1362z_256x64_init_seq);
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break;
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*/
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case U8X8_MSG_DISPLAY_SET_POWER_SAVE:
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if ( arg_int == 0 )
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u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1362z_powersave0_seq);
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else
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u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1362z_powersave1_seq);
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break;
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#ifdef U8X8_WITH_SET_CONTRAST
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case U8X8_MSG_DISPLAY_SET_CONTRAST:
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u8x8_cad_StartTransfer(u8x8);
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u8x8_cad_SendCmd(u8x8, 0x081 );
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u8x8_cad_SendArg(u8x8, arg_int ); /* ssd1362z has range from 0 to 255 */
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u8x8_cad_EndTransfer(u8x8);
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break;
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#endif
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case U8X8_MSG_DISPLAY_DRAW_TILE:
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u8x8_cad_StartTransfer(u8x8);
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x = ((u8x8_tile_t *)arg_ptr)->x_pos;
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x *= 4; // convert from tile pos to display column
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x += u8x8->x_offset;
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y = (((u8x8_tile_t *)arg_ptr)->y_pos);
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y *= 8;
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u8x8_cad_SendCmd(u8x8, 0x075 ); /* set row address, moved out of the loop (issue 302) */
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u8x8_cad_SendArg(u8x8, y);
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u8x8_cad_SendArg(u8x8, y+7);
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do
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{
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c = ((u8x8_tile_t *)arg_ptr)->cnt;
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ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;
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do
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{
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u8x8_cad_SendCmd(u8x8, 0x015 ); /* set column address */
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u8x8_cad_SendArg(u8x8, x ); /* start */
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u8x8_cad_SendArg(u8x8, x+3 ); /* end */
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u8x8_cad_SendData(u8x8, 32, u8x8_ssd1362z_oel1m0033we_8to32(u8x8, ptr));
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ptr += 8;
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x += 4;
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c--;
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} while( c > 0 );
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arg_int--;
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} while( arg_int > 0 );
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u8x8_cad_EndTransfer(u8x8);
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break;
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default:
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return 0;
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}
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return 1;
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}
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/*=========================================================*/
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static const uint8_t u8x8_d_ssd1362z_256x64_flip0_seq[] = {
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U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
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U8X8_CA(0xa0, 0xc3), //Set Remap c3 = 11000011
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U8X8_END_TRANSFER(), /* disable chip */
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U8X8_END() /* end of sequence */
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U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
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U8X8_C(0xAF), /* ssd1362z: display on */
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U8X8_END_TRANSFER(), /* disable chip */
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U8X8_END() /* end of sequence */
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};
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static const uint8_t u8x8_d_ssd1362z_256x64_flip1_seq[] = {
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U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
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U8X8_CA(0xa0, 0xd0),
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U8X8_END_TRANSFER(), /* disable chip */
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U8X8_END() /* end of sequence */
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static const uint8_t u8x8_d_ssd1362z_powersave1_seq[] =
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{
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U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
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U8X8_C(0xAE), /* ssd1362z: display off */
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U8X8_END_TRANSFER(), /* disable chip */
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U8X8_END() /* end of sequence */
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};
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static const uint8_t u8x8_d_ssd1362z_256x64_flip0_seq[] =
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{
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U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
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U8X8_CA(0xA0, 0xC1), /* Set Remap C1 = 11000001 */
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U8X8_END_TRANSFER(), /* disable chip */
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U8X8_END() /* end of sequence */
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};
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static const uint8_t u8x8_d_ssd1362z_256x64_flip1_seq[] =
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{
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U8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */
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U8X8_CA(0xA0, 0xD1), /* Set Remap D1 = 11010001 */
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U8X8_END_TRANSFER(), /* disable chip */
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U8X8_END() /* end of sequence */
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};
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static const uint8_t u8x8_d_ssd1362z_256x64_init_seq[] =
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{
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U8X8_START_TRANSFER(), // enable chip, delay is part of the transfer start
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U8X8_CA(0xFD, 0x12), // unlock
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U8X8_C(0xAE), // set display off
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U8X8_CA(0x81, 0x7F), // set contrast: 127
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U8X8_CA(0xA0, 0xC1), // set re-map
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U8X8_CA(0xA1, 0x00), // set display start line
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U8X8_CA(0xA2, 0x00), // set display offset
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U8X8_C(0xA4), // set display mode: normal
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U8X8_CA(0xA8, 0x3F), // set multiplex ratio: (63 rows)
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U8X8_CA(0xAB, 0x01), // set VDD regulator: enable
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U8X8_CA(0xAD, 0x9E), // set Iref selection, 9E: internal, 8E: external
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U8X8_CA(0xB1, 0x22), // set phase length
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U8X8_CA(0xB3, 0xA0), // set front clock divider/oscillator frequency
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U8X8_CA(0xB6, 0x04), // set second precharge period
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U8X8_C(0xB9), // set linear LUT
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U8X8_CA(0xBC, 0x04), // set pre-charge voltage level
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U8X8_CA(0xBD, 0x00), // set pre-charge voltage capacitor selection, 0: without, 1: with Vp capacitor
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U8X8_CA(0xBE, 0x05), // set COM deselect voltage level
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U8X8_C(0xAF), // set display on
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U8X8_END_TRANSFER(), // disable chip
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U8X8_END() // end of sequence
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};
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static const u8x8_display_info_t u8x8_ssd1362z_oel1m0033we_256x64_display_info =
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{
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/* chip_enable_level = */ 0,
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/* chip_disable_level = */ 1,
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/* post_chip_enable_wait_ns = */ 20,
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/* pre_chip_disable_wait_ns = */ 10,
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/* reset_pulse_width_ms = */ 100, /* ssd1362z: 2 us */
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/* post_reset_wait_ms = */ 100, /* far east OLEDs need much longer setup time */
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/* sda_setup_time_ns = */ 50, /* ssd1362z: 15ns, but cycle time is 100ns, so use 100/2 */
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/* sck_pulse_width_ns = */ 50, /* ssd1362z: 20ns, but cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */
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/* sck_clock_hz = */ 10000000UL, /* since Arduino 1.6.0, the SPI bus speed in Hz. Should be 1000000000/sck_pulse_width_ns, increased to 8MHz (issue 215), 10 MHz (issue 301) */
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/* spi_mode = */ 0, /* active high, rising edge */
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/* i2c_bus_clock_100kHz = */ 4,
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/* data_setup_time_ns = */ 10,
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/* write_pulse_width_ns = */ 150, /* ssd1362z: cycle time is 300ns, so use 300/2 = 150 */
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/* tile_width = */ 32, /* 256 pixel, so we require 32 bytes for this */
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/* tile_height = */ 8,
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/* default_x_offset = */ 0, /* this is the byte offset (there are two pixel per byte with 4 bit per pixel) */
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/* flipmode_x_offset = */ 0,
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/* pixel_width = */ 256,
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/* pixel_height = */ 64
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};
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static const uint8_t u8x8_d_ssd1362z_256x64_init_seq[] = {
|
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/* chip_enable_level = */ 0,
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/* chip_disable_level = */ 1,
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|
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U8X8_DLY(1),
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U8X8_START_TRANSFER(), // enable chip, delay is part of the transfer start
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U8X8_DLY(1),
|
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|
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U8X8_CA(0xfd, 0x12), // unlock
|
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U8X8_C(0xae), // display off
|
||||
U8X8_CA(0x81, 0x7f), // Set contrast: 127
|
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U8X8_CA(0xa0, 0xc1),
|
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U8X8_CA(0xa1, 0x00), // Set Display Start Line
|
||||
U8X8_CA(0xa2, 0x00), // Set Display Offset
|
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U8X8_C(0xa4), // Normal Display
|
||||
U8X8_CA(0xa8, 0x3f), // Set Multiplex Ratio: (63 rows)
|
||||
U8X8_CA(0xab, 0x01), // Enable VDD regulator
|
||||
U8X8_CA(0xad, 0x9e), // External /Internal IREF Selection, 9e: internal, 8e: external
|
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U8X8_CA(0xb1, 0x22), // Set Phase Length
|
||||
U8X8_CA(0xb3, 0xa0), // Display clock Divider
|
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U8X8_CA(0xb6, 0x04), // Set Second precharge Period
|
||||
U8X8_C(0xb9), // Set Linear LUT
|
||||
U8X8_CA(0xbc, 0x04), // Set pre-charge voltage level, 0..0x1f, 0x04 = 0.15*VCC
|
||||
U8X8_CA(0xbd, 0x00), // Pre-charge voltage capacitor Selection, 0: without, 1: with Vp capacitor
|
||||
U8X8_CA(0xbe, 0x05), // Set COM deselect voltage level, 5 = 0.82*VCC
|
||||
U8X8_DLY(1), // delay 1ms
|
||||
|
||||
U8X8_END_TRANSFER(), // disable chip
|
||||
U8X8_END() // end of sequence
|
||||
/* post_chip_enable_wait_ns = */ 50,
|
||||
/* pre_chip_disable_wait_ns = */ 20,
|
||||
/* reset_pulse_width_ms = */ 2, /* ssd1362z: 2 us */
|
||||
/* post_reset_wait_ms = */ 10, /* far east OLEDs need much longer setup time */
|
||||
/* sda_setup_time_ns = */ 50, /* ssd1362z: 15ns, but cycle time is 100ns, so use 100/2 */
|
||||
/* sck_pulse_width_ns = */ 50, /* ssd1362z: 20ns, but cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */
|
||||
/* sck_clock_hz = */ 10000000UL, /* since Arduino 1.6.0, the SPI bus speed in Hz. Should be 1000000000/sck_pulse_width_ns, increased to 8MHz (issue 215), 10 MHz (issue 301) */
|
||||
/* spi_mode = */ 0, /* active high, rising edge */
|
||||
/* i2c_bus_clock_100kHz = */ 4,
|
||||
/* data_setup_time_ns = */ 10,
|
||||
/* write_pulse_width_ns = */ 150, /* ssd1362z: cycle time is 300ns, so use 300/2 = 150 */
|
||||
/* tile_width = */ 32, /* 256 pixel, so we require 32 bytes for this */
|
||||
/* tile_height = */ 8,
|
||||
/* default_x_offset = */ 0, /* this is the byte offset (there are two pixel per byte with 4 bit per pixel) */
|
||||
/* flipmode_x_offset = */ 0,
|
||||
/* pixel_width = */ 256,
|
||||
/* pixel_height = */ 64
|
||||
};
|
||||
|
||||
/*
|
||||
input: one tile (8 Bytes)
|
||||
output: Tile for SSD1362Z (32 Bytes)
|
||||
*/
|
||||
|
||||
static uint8_t u8x8_ssd1362z_oel1m0033we_convert_buf[32];
|
||||
|
||||
static uint8_t *u8x8_ssd1362z_oel1m0033we_8to32(U8X8_UNUSED u8x8_t *u8x8, uint8_t *ptr)
|
||||
{
|
||||
uint8_t i, j;
|
||||
uint8_t a, b;
|
||||
uint8_t *dest;
|
||||
|
||||
for (j = 0; j < 4; j++)
|
||||
{
|
||||
dest = u8x8_ssd1362z_oel1m0033we_convert_buf + j;
|
||||
a = *ptr++;
|
||||
b = *ptr++;
|
||||
for (i = 0; i < 8; i++)
|
||||
{
|
||||
uint8_t v = 0;
|
||||
if (a & 1) v |= 0xF0;
|
||||
if (b & 1) v |= 0x0F;
|
||||
*dest = v;
|
||||
dest += 4;
|
||||
a >>= 1;
|
||||
b >>= 1;
|
||||
}
|
||||
}
|
||||
|
||||
return u8x8_ssd1362z_oel1m0033we_convert_buf;
|
||||
}
|
||||
|
||||
uint8_t u8x8_d_ssd1362z_common(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)
|
||||
{
|
||||
switch(msg)
|
||||
{
|
||||
case U8X8_MSG_DISPLAY_SET_POWER_SAVE:
|
||||
if ( arg_int == 0 )
|
||||
u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1362z_powersave0_seq);
|
||||
else
|
||||
u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1362z_powersave1_seq);
|
||||
break;
|
||||
case U8X8_MSG_DISPLAY_SET_FLIP_MODE:
|
||||
if ( arg_int == 0 )
|
||||
{
|
||||
u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1362z_256x64_flip0_seq);
|
||||
u8x8->x_offset = u8x8->display_info->default_x_offset;
|
||||
}
|
||||
else
|
||||
{
|
||||
u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1362z_256x64_flip1_seq);
|
||||
u8x8->x_offset = u8x8->display_info->flipmode_x_offset;
|
||||
}
|
||||
break;
|
||||
#ifdef U8X8_WITH_SET_CONTRAST
|
||||
case U8X8_MSG_DISPLAY_SET_CONTRAST:
|
||||
u8x8_cad_StartTransfer(u8x8);
|
||||
u8x8_cad_SendCmd(u8x8, 0x81);
|
||||
u8x8_cad_SendArg(u8x8, arg_int);
|
||||
u8x8_cad_EndTransfer(u8x8);
|
||||
break;
|
||||
#endif
|
||||
case U8X8_MSG_DISPLAY_DRAW_TILE:
|
||||
{
|
||||
u8x8_tile_t *tile = (u8x8_tile_t *)arg_ptr;
|
||||
uint8_t y = tile->y_pos * 8;
|
||||
uint8_t v_tiles = arg_int;
|
||||
|
||||
u8x8_cad_StartTransfer(u8x8);
|
||||
u8x8_cad_SendCmd(u8x8, 0x75);
|
||||
u8x8_cad_SendArg(u8x8, y);
|
||||
u8x8_cad_SendArg(u8x8, y + 7);
|
||||
do
|
||||
{
|
||||
uint8_t x = tile->x_pos * 4 + u8x8->x_offset;
|
||||
uint8_t c = tile->cnt;
|
||||
uint8_t *ptr = tile->tile_ptr;
|
||||
|
||||
do
|
||||
{
|
||||
u8x8_cad_SendCmd(u8x8, 0x15);
|
||||
u8x8_cad_SendArg(u8x8, x);
|
||||
u8x8_cad_SendArg(u8x8, x + 3);
|
||||
u8x8_cad_SendData(u8x8, 32, u8x8_ssd1362z_oel1m0033we_8to32(u8x8, ptr));
|
||||
ptr += 8;
|
||||
x += 4;
|
||||
c--;
|
||||
}
|
||||
while (c > 0);
|
||||
|
||||
v_tiles--;
|
||||
tile->y_pos++;
|
||||
}
|
||||
while (v_tiles > 0);
|
||||
|
||||
u8x8_cad_EndTransfer(u8x8);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
uint8_t u8x8_d_ssd1362z_256x64_oel1m0033we(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)
|
||||
{
|
||||
switch(msg)
|
||||
{
|
||||
case U8X8_MSG_DISPLAY_SETUP_MEMORY:
|
||||
u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1362z_oel1m0033we_256x64_display_info);
|
||||
break;
|
||||
case U8X8_MSG_DISPLAY_INIT:
|
||||
u8x8_d_helper_display_init(u8x8);
|
||||
u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1362z_256x64_init_seq);
|
||||
break;
|
||||
case U8X8_MSG_DISPLAY_SET_FLIP_MODE:
|
||||
if ( arg_int == 0 )
|
||||
{
|
||||
u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1362z_256x64_flip0_seq);
|
||||
u8x8->x_offset = u8x8->display_info->default_x_offset;
|
||||
}
|
||||
else
|
||||
{
|
||||
u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1362z_256x64_flip1_seq);
|
||||
u8x8->x_offset = u8x8->display_info->flipmode_x_offset;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
return u8x8_d_ssd1362z_common(u8x8, msg, arg_int, arg_ptr);
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
switch(msg)
|
||||
{
|
||||
case U8X8_MSG_DISPLAY_SETUP_MEMORY:
|
||||
u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1362z_oel1m0033we_256x64_display_info);
|
||||
break;
|
||||
case U8X8_MSG_DISPLAY_INIT:
|
||||
u8x8_d_helper_display_init(u8x8);
|
||||
u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1362z_256x64_init_seq);
|
||||
break;
|
||||
default:
|
||||
return u8x8_d_ssd1362z_common(u8x8, msg, arg_int, arg_ptr);
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user